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The quadrature modulators and demodulators are widely used to create modern wireless communication systems. It is important to ensure high quality of the transmitted signals in order to have the exchange of information without loss or failure. From the point of view of the spectral decomposition of the signal (Fourier series decomposition), the useful component of the spectrum must be much larger than all other components. The carrier (LO frequency and spurious sideband are the most critical and undesirable quadrature modulator output signal spectral components. In the work, in the course of the research using the methods of suppressing the parasitic components, based on minimizing phase, amplitude and current imbalances in various nodes of the quadrature modulator circuit, have been revealed. In order to realize suppression, the special digital-to-analog converters are used in conjunction with a polyphase filter on varicaps, a phase-shifting block and current sources. The effectiveness of these methods is confirmed by the achievement of suppression of parasitic components in prototypes of 50 dB or more. It has been stated that the phase unbalance minimization is more effective than the amplitude unbalance minimization to sideband suppression. It has been revealed that the use of a phase-shifting block is a more suitable architecture to control the phase unbalance. The obtained results can be useful in the design of high-precision radio frequency units for various purposes.

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The trends in development of the scientific-educational programs in designing microelectronic devices have been considered, and the significance of involving students and PhD. post-graduates in scientific projects has been underlined. The problems of the standard cell libraries development have been investigated, the automation approaches based on the parametric cells and the application of the optimization methods have been proposed. The prototype of the inverter standard cell, created in accordance with the above theoretical basis, has been presented.

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It is necessary to reduce the configuration bit stream volume if there is a need to write several FPGA configurations to the ROM. This leads to decrease in the topological size of the ROM block on the chip. The article discusses the development of the mechanism of compression and decompression of the FPGA configuration bit stream. It has been shown that the stream of configuration data has some regularities. This is due to the presence of a large number of «forbidden» states in the configuration data set, when inadmissible connections of logical elements are formed. The algorithm of compression and decompression of the FPGA configuration bit stream has been proposed. The algorithm is based on the analysis of the FPGA architecture and the compilation of the conversion table using the prefix code commands. The advantage of the algorithm is the search for the most repetitive combinations based on the analysis of the FPGA architecture, instead of searching for the entropy of a random set of configuration data. Another advantage is the relative simplicity of the decoding algorithm, which saves hardware resources for the implementation of the decompression mechanism.

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There are certain difficulties in the development of a broadband generator of quadrature signals (QSG) on a SiGe BiCMOS technology. The problem of linearity and broadband matching is the most difficult to solve. When designing QSG in a wide frequency band, there is a problem of forming a quadrature signal using traditional solutions using a polyphase filter or a digital D-trigger. The use of only one method for forming a quadrature signal is impossible due to the limiting features of the electronic component base of SiGe BiCMS technology. To solve this problem, we propose a structure that allows us to develop a broadband quadrature signal generator with an operating frequency range from 10 MHz to 6 GHz, using the method of dividing the operating frequency band. At frequencies from 1 to 6 GHz, the quadrature signal is generated using a polyphase filter, and at frequencies less than 1 GHz using a frequency divider. Using this method, the following characteristics of the FCS have been achieved: the difference in the amplitudes of quadrature signals is less than 0.3 dB; the VSWR is less than 1.6 over the entire frequency range; the transmission coefficient is not less than -2 dB at a 0 dBm heterodyne power; at a frequency of 6 GHz P1dB of at least 3 dBm. The experimental results are in good agreement with the simulation data.

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A formalized method of automated bandgap reference source design has been proposed. The distinctive feature of the method is the automation of the synthesis process of circuit engineering presentation, which considerably reduces the design time. Based on the developed methods in the SOI 180 nm technology the circuit has been designed. It has been shown that the obtained circuit engineering solution has the required characteristics: the power supply rejection ratio at 1 kHz in the worst case is -60 dB, at 1 MHz -44 dB, the maximum consumed current is 25 uA, the temperature coefficient is 24 ppm/°C in the temperature range from -70 to 150 °C, the line regulation is 354 uV/V in the supply voltage range from 2.4 to 7 V.

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For creating an optimal in terms of speed and flexibility programming the FPGA switching block it is necessary to estimate the minimum number of the commutation switches and their location in the connection matrix. In the work the problems of designing and evaluating the structure of the FPGA switching block have been considered. The algorithm for constructing and evaluating the structure of the FPGA switching blocks with the number of the interblock connections, based on the graph theory and combinatorial analysis, has been developed. It has been shown that not only the number of keys provides the commutation efficiency, but, also their location method.

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The principal embodiments of implementing the circuit of serial access to flash-memory have been considered. The advantages and drawbacks of existing solutions have been analyzed. A new option of the circuit of serial access to flash-memory with eliminating the lacks inherent in the existing solutions has been presented.

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The main variants of simulation transistors with a floating gate have been reviewed. A new method for modeling the analog transistor with a floating gate, taking into account a discrete spectrum of the charge state on the floating gate has been presented. The method permits to reduce the modeling time, to lower the requirements to the resources (libraries and design tools) and provides the compromise accuracy of the calculation.

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