Algorithm for Compression and Decompression of the FPGA Configuration Bit Stream

Algorithm for Compression and Decompression of the FPGA Configuration Bit Stream

It is necessary to reduce the configuration bit stream volume if there is a need to write several FPGA configurations to the ROM. This leads to decrease in the topological size of the ROM block on the chip. The article discusses the development of the mechanism of compression and decompression of the FPGA configuration bit stream. It has been shown that the stream of configuration data has some regularities. This is due to the presence of a large number of «forbidden» states in the configuration data set, when inadmissible connections of logical elements are formed. The algorithm of compression and decompression of the FPGA configuration bit stream has been proposed. The algorithm is based on the analysis of the FPGA architecture and the compilation of the conversion table using the prefix code commands. The advantage of the algorithm is the search for the most repetitive combinations based on the analysis of the FPGA architecture, instead of searching for the entropy of a random set of configuration data. Another advantage is the relative simplicity of the decoding algorithm, which saves hardware resources for the implementation of the decompression mechanism.
Igor V. Kuzminov
National Research University of Electronic Technology, Moscow, Russia; Joint Stock Company «Molecular Electronics Research Institute», Moscow, Russia
Vladimir V. Losev
National Research University of Electronic Technology, Moscow, Russia
Ivan S. Novozhilov
National Research University of Electronic Technology, Moscow, Russia; JSC «Molecular Electronics Research Institute», Moscow, Russia
Yury A. Chaplygin
National Research University of Electronic Technology, Moscow, Russia
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