Persons

The problem of analyzing and evaluating the structure of FPGA routing resources at early stages of the design flow presents great interest for researchers. Until now, an approach, consisting in passing the full design flow (logic synthesis, placement, routing) on a set of the test circuits with subsequent estimation of various parameters for each FPGA architecture being analyzed, had been dominant. Despite the high accuracy, this approach has a long runtime and requires lots of computing resources, as well as CAD tuned to the analyzed FPGA architecture. Modern FPGA contain more than a million logical gates, therefore, the application of such approach is inefficient. Today, more attention is paid to the development of various models, which allows to evaluate the structure of the routing resources at early stages without using the benchmark circuits. In this work an overview of the existing models and methods for analyzing the structure of FPGA routing resources has been presented. A comparison of the methods and models has been performed, the estimation of their efficiency and possibility of application for designing domestic FPGA has been made. It has been found that the most optimal approach for analyzing of arbitrary structures of the routing resources FPGA is the development and application of mixed methods. This will allow to obtain the accurate models as well as to significantly reduce the development and market entry time.

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The logic and timing analysis problems for design and optimization of VLSI IP-blocks have been considered. A new logic-timing simulation approach, which uses the interval estimation, has been proposed for CMOS circuits. The proposed approach unites two opposite methods of the timing analysis, such as the critical path search and input stimulus simulation. The interval approach has been chosen due to considerable variation increasing effect for the nanometer elements performance analysis.

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Currently, the methods based on a Boolean satisfiability (SAT) problem are one of the efficient approaches to solving the problem of Boolean matching and the equivalence checking of digital circuits. In combination with classic routing algorithms and optimization techniques, the SAT methods demonstrate the results exceeding the classic routing algorithms by the operation speed and the quality of obtained results. In the paper, the analysis of the modern practice of using the SAT methods in the CAD systems for VLSI has been performed. The examples of modern SAT approaches to the problems of the formal equivalence checking of digital circuits descriptions within the technological mapping framework and to the routing problem as a part of the FPGA design flow have been considered. The algorithm of the detailed routing of the FPGA switching blocks using the satisfiability problem has been developed and presented. The results of its work have been demonstrated on the example of the programmable logic block of the domestic made integrated circuit 5400TP094. The block has the island architecture, where the configurable logic blocks and switching blocks form a regularly repeated layout template. The properties of the chosen classic architecture permit to expand the region of presented algorithm to the entire class of island style FPGA. The algorithm has been tested on the project benchmarks ISCAS-85, ISCAS-89 and LGSynth-89. The comparison of the developed SAT-based algorithm with the well-known routing algorithm Pathfinder by criteria of the elapsed time and the achieved portion of routed nets in the switching blocks is presented. It has been determined that the considered Boolean satisfiability methods for the routing problem are capable to prove the circuit unroutability, unlike the algorithm Pathfinder which results can only implicitly indicate it. The paper demonstrates that the application of more efficient SAT solver significantly accelerates work of the suggested detailed routing algorithm.

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Intellectual Property (IP) cores are developed and used to accelerate the custom integrated circuits design flow and improve their final characteristics. There are two types of FPGA IP-cores: hard IP-core and soft IP-core. Hard IP-cores have an exact location and pre-routed interconnects while soft IP-cores can be synthesized from logic elements and should be placed and routed. To use IP-cores in automated design flow of integrated circuits on FPGA and RSoC it is necessary to develop IP-core libraries that allow identifying blocks on every stage of flow. This work shows the various soft and hard IP-core libraries’ types and formats used as a part of design flow for Russian FPGA and RSoC. It describes the methods of designing libraries needed by CAD systems at the stages of logic synthesis, automatic technological mapping and layout synthesis. Also, it considers soft and hard IP-core libraries’ distinct features and the methods of their formation adjusted for the FPGA and RSoC architecture. The design methods have been proposed that allow designing of libraries necessary for automated implementation of hard as well as soft IP-cores using advantage of base FPGA and RSoC architecture.

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The modem problems of the logical and timing analyses, which occur during the characterization of the CMOS VLSI blocks, have been considered. To solve this problem, the generalized logical-timing model of the functional block has been proposed. Such model, using the SP-DAG structure, includes both the logical function and the hierarchical representation of the circuit given at the transistor level. The Gaussian elimination method for the block generalized model extraction from the circuit netlist has been proposed. The estimation of conductance and capacitance values, as well as the delay analysis has been performed on the basis of the proposed model. Also, the branch and bound algorithm, enabling designers to verify the delays for a big number of different input patterns without the need of electrical simulation, has been proposed.

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The problems of the statistical analysis of complex functional blocks have been considered. The methods of the statistical analysis and the simulation speedup have been analyzed. The approach, that allows a considerable reduction of the computational costs during the statistical simulation of the complex functional blocks, has been proposed. The proposed approach is based on using the models of the circuit functional parameters, which are calculated as the quadratic forms with the rank 1 matrix. The comparative analysis results are shown for the cases when the linear regression and the least-squares regression are used during the degeneration of the models for the functional parameters of the complex functional blocks.

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One of the main advantages of FPGA and CPLD is the high development speed; therefore, the importance of effective computer-aided design tools for modern microcircuits of these classes cannot be overestimated. Placement and routing are the most time-consuming stages of FPGA/CPLD design flow. The quality of results of these stages is crucial to the final performance of custom digital circuits implemented on FPGA/CPLD. The paper discusses an approach to accelerating the routing stage within the layout synthesis flow for FPGA/CPLD by introducing a few algorithmic improvements to a routing procedure. The basic routing algorithm under study is a modified Pathfinder for a mixed routing resource graph. Pathfinder is a well-known negotiation-based routing algorithm that works on the principle of iteratively eliminating congestions of chip routing resources. For experiments, the sets of test digital circuits ISCAS'85, ISCAS'89, LGSynth'89 and several custom industrial projects were used. The impact of the proposed algorithmic improvements was analyzed using four FPGA/CPLD architectures. It has been established that due to the improvements of the algorithm proposed in the paper, the average reduction in routing time was from 1.3 to 2.6 times, depending on the FPGA/CPLD architecture, with no significant negative effect on the timing characteristics of the designed circuits.

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Searching for new ways to improve the efficiency of integrated circuits (IC) led to the development of specialized heterogeneous configurable IC (FPGA) and systems-on-a-chip. Their key feature is an extended interpretation of standard cell library, containing ready-to-use IP cores along with standard cells. Specific customer designs require the flexibility of the configurable heterogeneous IC’s architecture and, therefore, automatic CAD clustering and placement algorithms configuration. The development of efficient configuration methods and algorithms is impossible without relying on the mathematical apparatus. In this work, such mathematical apparatus is provided. The authors described a set-theoretic model of a hierarchical project and formalized the hierarchical approach to the netlist, using the apparatus of mathematical logic, set and graph theories. The correspondence between the customers designs’ elements and FPGA’s elements has been formalized to provide fast clustering and placement configuration. The obtained results provide the basis for future efficient methods for automatic placement and clustering configuration.

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The problems of the standard cell libraries simulation and characterization designed on the basis of the deep semiconductor CMOS technologies of the submicron and nanometer level have been considered. The methods for accelerating the characterization process, providing the identification of parameters for the macro-models of logic elements during multiple simulation of the elements on the circuit engineering level for different input impacts and different values of technological parameters and operating condition have been analyzed. The optimal characterization grid search algorithms have been proposed for the purpose of computational resources reduction under the required macro-model accuracy control. The comparison results for different modes of the proposed algorithms have been presented.

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The transition to the level of the nanometer technologies leads to the new field in nanoelectronics, specifically the design based on the CMOS technology with 3D structure of the transistor. With decrease the size of transistors up to 32 nm and lower the application of FinFET technology becomes one of few methods to increase speed and to decrease the power consumption. This direction changes the design route and requires the development of new approaches, both in the logical and topological design. The traditional approach is based on the independent solution of the problems on the logical and physical levels. However, the combination of the logical and topological synthesis results in a significant increase of the problem dimension, which, in its turn, affects the designing time. The algorithm of the logical analysis and synthesis of microchip circuits with application of the FinFET technology while simultaneous solving the problems of the logical and topological synthesis has been developed. It has been offered to introduce the restrictions for the topological realization in simultaneous solving the problems of the logical and topological synthesis. The restrictions have been obtained from the regular topological template with a fixed layout in the lower layers. The proposed approach allows a hundreds to thousands times reduction of the design rules number, and the application of the IG FinFET transistors provides the best speed and power performances compared to the standard CMOS technology.

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The existing means for designing automation are oriented, mainly, at technologies of western manufactures. As a result, a need in adaptation of available methods and means of designing the reconfigurable systems on chip and development of domestic specialized CAD devices for solving the actual tasks in this field appears. The methods for solving the interconnect routing problems combined with the logical resynthesis, considering the architecture of the reconfigurable system-on-chip (RSoC) based on FPGA of Almaz-14, have been proposed. In the chip the developers from JSC «NIIME» and PJSC «Micron» have created an extensive configuration options having no foreign analogs. The availability of a wide range of additional elements for configuring as well as the capabilities of logical resynthesis of the FPGA Almaz-14 microcircuit leads to the necessity of developing the new methods for routing the interconnects, which could take into account and use these architectural features. The efficient algorithm of automatic routing of interconnects for RSoC based on FPGA of Almaz-14 series based on the algorithm A*, of the modification of a classical algorithm of searching for the shortest path on graph, the Dijkstra’s algorithm, including the model of the mixed commutation graph, has been developed. For description of the variety of additional switching elements a special generalized mathematical model as well as a special command interface in Tcl language, which includes a list of configuration elements, their description and functionality, has been developed. The of result of the work is an improvement of the automated design efficiency using the developed and implemented in C language for optimal use of the configurations and route elements of FPGA, as well as of the mechanisms for the full and correct routing of interconnects.

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