The problems of the standard cell libraries simulation and characterization designed on the basis of the deep semiconductor CMOS technologies of the submicron and nanometer level have been considered. The methods for accelerating the characterization process, providing the identification of parameters for the macro-models of logic elements during multiple simulation of the elements on the circuit engineering level for different input impacts and different values of technological parameters and operating condition have been analyzed. The optimal characterization grid search algorithms have been proposed for the purpose of computational resources reduction under the required macro-model accuracy control. The comparison results for different modes of the proposed algorithms have been presented.