The modem problems of the logical and timing analyses, which occur during the characterization of the CMOS VLSI blocks, have been considered. To solve this problem, the generalized logical-timing model of the functional block has been proposed. Such model, using the SP-DAG structure, includes both the logical
function and the hierarchical representation of the circuit given at the transistor level. The Gaussian elimination method for the block generalized model extraction from the circuit netlist has been proposed. The estimation of conductance and capacitance values, as well as the delay analysis has been performed on the basis of the proposed model. Also, the branch and bound algorithm, enabling designers to verify the delays for a big number of different input patterns without the need of electrical simulation, has been proposed.
1. Bryant R.E. Graph-based algorithms for boolean function manipulation // IEEE Trans. Computers. - 1986. - Р. 677-691.
2. Bryant R.E. Algorithmic aspects of symbolic switch network analysis // IEEE Trans. оп CAD. - 1987. - Р. 618-633.
3. Bryant R.E. Boolean analysis of MOS circuits // IEEE Trans. оп CAD. - 1987. - Р. 634-649.
4. Qin Z., Cheng С.-К. Realizable parasitic reduction using generalized Y-Δ transformation // Proc. of DAC, 2003. - Р. 220-225.
5. Amin C.S., Chowdhury М.Н., Ismail Y.I. Realizable RLCK circuit crunching // Proc. of DAC. - 2003. - Р. 226-231.
6. Sheehan B.N. TICER: Realizable reduction of extracted RC circuits // Digest of Technical Papers, IEEE/ACM Proc. of ICCAD. - 1999. - Р. 200-203.
7. Pillage L.Т., Rohrer R.A. Asymptotic waveform evaluation for timing Analysis // IEEE Trans. оп CAD. - 1990. - Vol. 9, N 4. - Р. 352-366.
8. Odabasioglu А., Celik М., аnd Pillegi L.Т. PRIMA: Passive reduced-order interconnect macromodeling Algorithm // IEEE Trans. оп CAD. - 1998. - Р. 645-654.