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Combinational adder performing arithmetic addition of binary numbers is an important architectural component in the implementation of operating devices of many modern microprocessors. To increase the performance of these operating devices an efficient adder is needed. Therefore, development of an effective adder providing high performance for devices of processors is an important task. Currently, parallel-prefix adders (PPA) are considered effective and are used for high speed addition of two multi-bit binary numbers. Several PPAs with different time and hardware characteristics are known. Among these adders, Kogge - Stone adder has the highest speed than other PPAs. However, its disadvantages are the use of a larger number of logical elements and, therefore, the use of a larger area, which leads to an increase in its price. In this paper, the Kogge - Stone adder has been analyzed. To reduce its hardware and time costs, a modified parallel-prefix adder has been developed. Comparison of both adders has been performed according to the occupied area and the maximum delay in the operation. Scheme of result verification has been implemented to confirm the reliability of the proposed adder. Simulation of this scheme has been carried out in an Altera Quartus-II CAD environment. The results of this work show that when performing operations with 32-bit and 64-bit operands, the proposed adder reduces the occupied area by 11 % and 16.5 % and the maximum delay by 7 % than Kogge - Stone adder.

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In modern microprocessors to reduce the time resources the arithmetic-logic units (ALU) with an increased organization of arithmetic carry, characterized by high speed, compared to ALU with sequential organization of the arithmetic carry, are commonly used. However, while increasing the bit number of the input operands, the operating time of ALU of ALU with the accelerated arithmetic carry increases linearly depending on the number of bits. Therefore, the development of ALU, providing higher performance than the existing known solutions, is an actual task. In this work the analysis of ALU with sequential and accelerated organization of the arithmetic carry has been performed. To increase the speed of the operation, a multi-bit ALU has been developed. The simulation of ALU circuits has been executed in Altera Quartus -II CAD environment. The comparison has been performed by the number of logical elements and the maximum delay as a result of modeling the ALU circuits for 4, 8, 16, 32, and 64 bits. A scheme for checking the results has been implemented to confirm the reliability of developed ALU. As a result, it has been found that when performing operations with the 64-bit operands, the developed ALU reduces the maximum delay by 53 % compared to ALU with sequential arithmetic carry and by 35.5 % compared to ALU with the accelerated arithmetic carry, respectively. Keywords : ALU with sequential arithmetic carry; ALU with the accelerated arithmetic carry; ALU; arithmetic carry; number of logic elements; maximum delay

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The adder represents a logic operation unit, executing an arithmetic adding of two binary numbers in the arithmetic-logic devices being a part of the processors. Two types of the adders: single-bit and multibit ones have been distinguished. Depending on the scheme realization the adders have a compromise between the speed and the number of the logic elements being used. In this study a comparative analysis of the characteristics of the binary multibit parallel adders has been performed. Three architectures of parallel carry-propagate adders (CPA): ripple-carry adder (RCA), carry look-ahead adder CLA) and parallel prefix adder (PPA) have been studied. An optimal scheme of CPA using the comparative analysis of variants of schemes has been chosen by the characteristics with an increasing number of input bits. The analysis and synthesis of the adder schemes have been executed and the analytical expressions for constructing three CPA have been performed. The hardware implementations of single-bit adders and three CPA as well as the analysis of the number of logic elements and of the work speed with increasing the number of bits have been executed. The comparative analysis of parameters has shown that each adder has its own disadvantages and advantages. When building the 64-bit adder CPA gives a speed advantage of 65% with CLA and 88% compared with RCA. The comparison by the number of the logic elements shows that the advantage of RCA is 35% compared to CLA and 59% to PPA.

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The binary adders are the combinational nodes for performing the addition of the binary numbers in the arithmetic logic units included in many processors. Therefore, the design of an efficient binary adder is an actual task, which solution depends on the performance of existing device. Currently, a parallel-prefix adder is considered as effective for performing an addition of the two multi-bit binary numbers. There are several variants of the adder with different performance characteristics and hardware costs. In the work a modified variant of the parallel-prefix has been studied and the comparison of its parameters with Sklansky, Kogge-Stone, Brent-Kung and Lander-Fischer adders has been performed. The modeling of the adders has been made in the CAD Quartus II, and the comparative analysis of the adders has been executed by the hardware and time costs. The analysis of the simulation results shows that when the addition o 32-bit binary numbers is performed, the proposed adder has better performance compared to other adders considered, and, also, has 26%less complexity compared to the Kogge-Stone adder.

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