The binary adders are the combinational nodes for performing the addition of the binary numbers in the arithmetic logic units included in many processors. Therefore, the design of an efficient binary adder is an actual task, which solution depends on the performance of existing device. Currently, a parallel-prefix adder is considered as effective for performing an addition of the two multi-bit binary numbers. There are several variants of the adder with different performance characteristics and hardware costs. In the work a modified variant of the parallel-prefix has been studied and the comparison of its parameters with Sklansky, Kogge-Stone, Brent-Kung and Lander-Fischer adders has been performed. The modeling of the adders has been made in the CAD Quartus II, and the comparative analysis of the adders has been executed by the hardware and time costs. The analysis of the simulation results shows that when the addition o 32-bit binary numbers is performed, the proposed adder has better performance compared to other adders considered, and, also, has 26%less complexity compared to the Kogge-Stone adder.
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