The adder represents a logic operation unit, executing an arithmetic adding of two binary numbers in the arithmetic-logic devices being a part of the processors. Two types of the adders: single-bit and multibit ones have been distinguished. Depending on the scheme realization the adders have a compromise between the speed and the number of the logic elements being used. In this study a comparative analysis of the characteristics of the binary multibit parallel adders has been performed. Three architectures of parallel carry-propagate adders (CPA): ripple-carry adder (RCA), carry look-ahead adder CLA) and parallel prefix adder (PPA) have been studied. An optimal scheme of CPA using the comparative analysis of variants of schemes has been chosen by the characteristics with an increasing number of input bits. The analysis and synthesis of the adder schemes have been executed and the analytical expressions for constructing three CPA have been performed. The hardware implementations of single-bit adders and three CPA as well as the analysis of the number of logic elements and of the work speed with increasing the number of bits have been executed. The comparative analysis of parameters has shown that each adder has its own disadvantages and advantages. When building the 64-bit adder CPA gives a speed advantage of 65% with CLA and 88% compared with RCA. The comparison by the number of the logic elements shows that the advantage of RCA is 35% compared to CLA and 59% to PPA.
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