Combinational adder performing arithmetic addition of binary numbers is an important architectural component in the implementation of operating devices of many modern microprocessors. To increase the performance of these operating devices an efficient adder is needed. Therefore, development of an effective adder providing high performance for devices of processors is an important task. Currently, parallel-prefix adders (PPA) are considered effective and are used for high speed addition of two multi-bit binary numbers. Several PPAs with different time and hardware characteristics are known. Among these adders, Kogge - Stone adder has the highest speed than other PPAs. However, its disadvantages are the use of a larger number of logical elements and, therefore, the use of a larger area, which leads to an increase in its price. In this paper, the Kogge - Stone adder has been analyzed. To reduce its hardware and time costs, a modified parallel-prefix adder has been developed. Comparison of both adders has been performed according to the occupied area and the maximum delay in the operation. Scheme of result verification has been implemented to confirm the reliability of the proposed adder. Simulation of this scheme has been carried out in an Altera Quartus-II CAD environment. The results of this work show that when performing operations with 32-bit and 64-bit operands, the proposed adder reduces the occupied area by 11 % and 16.5 % and the maximum delay by 7 % than Kogge - Stone adder.
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