Persons

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Transition from planar MOSFET structures to FinFET 3D structures ensures various radiation type resistance. However, the characteristics of radiation-exposed devices made at different factories vary considerably and it is hard to explain FinFET structures’ radiation resistance dependence on variations of their physical and topological parameters and electrical modes. In this work, a RAD-TCAD model of FinFET on bulk silicon was developed. Additional semi-empirical radiation dependences specific to FinFET structures were introduced into the basic model of a nanometer MOSFET: the charge carrier effective mobility, the traps concentration in the SiO and HfO oxides and at the Si / SiO interface. The model was implemented in the Sentaurus Synopsys TCAD environment. The model was validated on a test set of FinFET structures with a channel length from 60 nm to 7 nm before and after exposure to gamma irradiation in the dose range up to 1 Mrad. Comparison of the modeled and experimental I-V characteristics has shown an error of no more than 15 %.

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The models of electro-physical effects built-into Sentaurus TCAD have been tested. The models providing an adequate modeling of deep submicron high-k MOSFETs have been selected. The gate and drain leakage currents for 45 nm MOSFET with PolySi gate and SiO, SiO/HfO and HfO gate dielectrics have been calculated using TCAD. It has been shown that the replacement of traditional SiO gate by an equivalent HfO dielectric considerably reduces the gate leakage current by several orders due to elimination of the tunneling effect influence. Besides, the threshold voltage, saturation drain current, mobility, transconductance, etc. degrade within 10-20% range.

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One of the base technologies in manufacturing of digital, analog and radio frequency VLSI and systems on sub-100 nm crystal is the CMOS technology with high-k under-gate dielectric. In present paper the effect of the ionizing radiation on n-channel 45 nm MOSFET transistors with high-k dielectric, manufactured by the on bulk silicon and «silicon on insulator» technologies, is being simulated. The effects, induced by the replacement of conventional dioxide from SiO to high-k dielectric, have been indicated. The selection and adjustment of the physical models for simulating high-k MOSFETs in the Synopsys TCAD have been described. The set of the new physical semi-empirical models accounting for TID dependences of oxide and HfO/Si interface trap densities, carrier mobility, the carrier lifetime has been developed and introduced into TCAD tool. The simulation of the nanoscale bulk and SOI MOSFETs with high-k dielectric has been carried out. It has been shown that for the nanometer SOI structures the increase in the drain current after irradiation is due to the accumulation of charge in the side oxide. An admissible agreement between the simulation results and experimental data has been achieved. The results confirm that the sub-100-nm CMOS technology with high-k dielectric compared to conventional CMOS technologies suppresses the drain current, however, for the rest important parameters it is more sensitive to the ionization radiation.

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The SOI MOSFET have the worst conditions of the heat removal from the active region, which negatively manifests itself on the reliability and efficiency of microcircuits. Using the TCAD modeling the self-heating effect has been investigated in the structures of deeply submicron MOSFETs with different configurations of the buried oxide: traditional bulk MOSFET and SOI structures, SELBOX structure, Partial SOI structure, thin-BOX SOI structure, UTBB SOI structure and Quasi-SOI structure. It has been shown that for a number of new designs the maximum temperature value in the MOSFET structure is significantly reduced in comparison with Tmax of the standard SOI MOSFET structure, approaching the typical values for standard MOSFETs on bulk silicon.

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