One of the base technologies in manufacturing of digital, analog and radio frequency VLSI and systems on sub-100 nm crystal is the CMOS technology with high-k under-gate dielectric. In present paper the effect of the ionizing radiation on n-channel 45 nm MOSFET transistors with high-k dielectric, manufactured by the on bulk silicon and «silicon on insulator» technologies, is being simulated. The effects, induced by the replacement of conventional dioxide from SiO to high-k dielectric, have been indicated. The selection and adjustment of the physical models for simulating high-k MOSFETs in the Synopsys TCAD have been described. The set of the new physical semi-empirical models accounting for TID dependences of oxide and HfO/Si interface trap densities, carrier mobility, the carrier lifetime has been developed and introduced into TCAD tool. The simulation of the nanoscale bulk and SOI MOSFETs with high-k dielectric has been carried out. It has been shown that for the nanometer SOI structures the increase in the drain current after irradiation is due to the accumulation of charge in the side oxide. An admissible agreement between the simulation results and experimental data has been achieved. The results confirm that the sub-100-nm CMOS technology with high-k dielectric compared to conventional CMOS technologies suppresses the drain current, however, for the rest important parameters it is more sensitive to the ionization radiation.
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