Persons

For digital microelectronic system design debugging, it is necessary to form a certain set of test influences on the simulated system to verify the correctness of its functioning. For a large number of digital systems, a sequence of functions from a finite alphabet is characteristic. It is shown that a partial semigroup is defined on the set of admissible sequences of functions. Valid sequences are formalized by introducing a graph of functions that defines the functions that can be performed for various states of the digital system. The function graph, together with the sets of input interactions for each function, specifies the specification of the external behavior of the digital system. If the admissibility of the sequential execution of two functions depends on previously performed functions and the state of the digital system, then some functions should be divided into subfunctions. It has been shown that a set of debugging tests should include both checking the execution of sequences of functions and the correctness of each function with various sets of parameters

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The logic and timing analysis problems for design and optimization of VLSI IP-blocks have been considered. A new logic-timing simulation approach, which uses the interval estimation, has been proposed for CMOS circuits. The proposed approach unites two opposite methods of the timing analysis, such as the critical path search and input stimulus simulation. The interval approach has been chosen due to considerable variation increasing effect for the nanometer elements performance analysis.

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The modem problems of the logical and timing analyses, which occur during the characterization of the CMOS VLSI blocks, have been considered. To solve this problem, the generalized logical-timing model of the functional block has been proposed. Such model, using the SP-DAG structure, includes both the logical function and the hierarchical representation of the circuit given at the transistor level. The Gaussian elimination method for the block generalized model extraction from the circuit netlist has been proposed. The estimation of conductance and capacitance values, as well as the delay analysis has been performed on the basis of the proposed model. Also, the branch and bound algorithm, enabling designers to verify the delays for a big number of different input patterns without the need of electrical simulation, has been proposed.

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