For digital microelectronic system design debugging, it is necessary to form a certain set of test influences on the simulated system to verify the correctness of its functioning. For a large number of digital systems, a sequence of functions from a finite alphabet is characteristic. It is shown that a partial semigroup is defined on the set of admissible sequences of functions. Valid sequences are formalized by introducing a graph of functions that defines the functions that can be performed for various states of the digital system. The function graph, together with the sets of input interactions for each function, specifies the specification of the external behavior of the digital system. If the admissibility of the sequential execution of two functions depends on previously performed functions and the state of the digital system, then some functions should be divided into subfunctions. It has been shown that a set of debugging tests should include both checking the execution of sequences of functions and the correctness of each function with various sets of parameters
1. Keresztes P., Tukacs A., Török M. A multi valued logic VHDL package for switch level simulation of novel digital CMOS Circuits // 2018 Inter. Conf. on Recent Innovations in Electrical, Electronics & Communication Engineering (Bhubaneswar, India, 2018). 2018. P. 25–28.
2. Lin Yi-Li, Su Alvin W.Y. Functional verification for SoC software/hardware Co-design: from virtual platform to physical platform // 2011 IEEE International SOC Conference. 2011. P. 201–206.
3. Software Hardware Co-Simulation and Co-Verification in Safety Critical System Design / Shi Jin, Liu, Weichao, Jiang Ming el al. // 2013 IEEE International Conference on Intelligent Rail Transportation. 2013.
P. 71–74.
4. Nguen M.D. Hardware/software formal co-verification using hardware verification techniques // Fourth Int. Conf. on Communications and Electronics. 2012. P. 465–470.
5. Выбор платформ прототипирования для СФ-блоков и подсистем СНК / Е.М. Абрамов, А.В. Егоров, А.О. Козлов и др. // Вопросы радиоэлектроники. 2017. № 8. С. 76–83.
6. Методы и алгоритмы для логико-топологического проектирования микроэлектронных схем на вентильном и межвентильном уровне для перспективных технологий с вертикальным затвором транзистора / Г.А. Иванова, Д.И. Рыжова, С.В. Гаврилов и др. // Микроэлектроника. 2019. Т. 48. № 3.
С. 201–210.
7. Иванников А.Д., Стемпковский А.Л. Формализация задачи отладки проектов цифровых систем // Информационные технологии. 2014. № 9. С. 3–10.
8. Оллонгрен А. Определение языков программирования интерпретирующими автоматами. М.: Мир, 1977. 288 с.
9. Мальцев А.И. Алгебраические системы. М.: Наука. 1970. 392 с.
10. Иванников А.Д. Формирование отладочного набора тестов для проверки функций цифровых систем управления объектами // Мехатроника, автоматизация, управление. 2017. Т. 18. № 12. С. 795–801.