Persons

Checker circuits are used for implementation of the device fault verification function. Boolean complement method is prospective for checker circuit synthesis for automation and computing devices. One of this method’s basic directions is computing control by code methods that imply fixed-length block code use at checker circuit synthesis. In this work, the error detection features by modular sum codes in codewords by multiplicities and error types (unidirectional, symmetrical and asymmetrical) are described. It is shown that an increase in the data vector length and the module increases the proportion of undetectable errors arising simultaneously in both data and check vectors, out of undetectable errors arising only in data vectors. For sum codes with modules M ≥ 4, this value exceeds 3. It has been suggested to consider the specified feature of modular sum codes in concurrent error-detection circuit synthesis in automation and computing devices using the Boolean complement method. For this purpose, it is necessary to separate in circuit the diagnostic object outputs, which form the data vector, and the diagnostic object outputs, including the check bits of the data vector. A decision rule has been formulated that allows this to be done for combinational devices. The experiment results with the concurrent error-detection circuit show the effectiveness of modular sum codes for concurrent error-detection circuit organizing using the Boolean complement method.

• Counter: 292 | Comments : 0

• Counter: 518 | Comments : 0