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During development and implementation of critical application devices and systems various ways are used to provide blocks, nodes, subsystems and systems with controllability, self-checking, fault-tolerance properties and fail-safe behavior. Different methods of information theory and coding are used during self-checking and fault-tolerant computing devices synthesis. In this work, the features of error detection by weight-based sum code, in which weight coefficients are assigned to pairs of successive bits of the data vector with intersection, are considered. The weight coefficients are taken from an increasing powers series of the number 2. Then a series of weight coefficients special permutations according to the described principles is done. Such codes called weight-based sum codes “with permutation” are referred to as Pm-codes (m – data vector length). The previously unknown properties of Pm-codes have been established, which should be considered in the development and synthesis of testable, self-checking and fault-tolerant computing devices and systems. The characteristics of detection by types and multiplicities of unidirectional, symmetrical, and asymmetrical errors arising from data and check vectors bits distortions are determined. It was demonstrated that despite the detecting property of any double errors in data vectors for small lengths of data vectors m < 10, Pm-codes cannot identify all double errors that occur when one data bit and one control bit are distorted. The experiment results on error detection by Pm-codes at the test combinational circuit outputs are presented. It is advisable to consider the established characteristics of error detection by Pm-codes in the accident-free fail-safe automation and computation devices synthesis tasks.
Dmitry V. Efanov
Russian University of Transport (Russia, 127994, Moscow, Obraztsov st., 9, bld.9)
Marina V. Zueva
“IBS Saint Petersburg” LLC (Russia, 190000, Saint Petersburg, Angliiskaya naberezhnaya st., 70)

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