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With the development of nanoelectronics, the requirements specified for precision in forming topological structures during IC manufacturing are becoming increasingly stringent. Particular importance is placed on photolithographic processes that determine the linear dimensions and shape of IC elements. However, one of the key factors limiting the achievement of the required high precision is the Line Edge Roughness (LER) effect, which manifests as random deviations of the boundaries of photoresist mask elements from an ideal shape. In this work, an analysis of the main causes of LER effect and of the results obtained using scanning electron microscopy and numerical simulation for quantitative evaluation of roughness parameters in the contours of photoresist mask elements at various stages of the lithographic process is performed. It was shown that even minimal deviations within 1–2 nm can significantly degrade the electrical characteristics of nanoscale transistors, especially at technology nodes below 28 nm. The analysis of potential technological techniques minimizing the manifestation of LER effect was performed. It has been demonstrated that identifying the causes of LER and developing the technologies to minimize its effects are crucial directions for ensuring the stability and performance of modern nanoelectronic devices, and a comprehensive approach to LER effect studying contributes to further advancements in the field of microelectronics.

Key words: Line Edge Roughness, LER effect, photoresist mask edge roughness, integrated circuits, ICs, photonic integrated circuits, PICs
Published in: TECHNOLOGICAL PROCESSES
Bibliography link: Kulpinov M. S., Putrya M. G., Golishnikov A. A., Balashov A. G. Causes of LER effect occurrence and methods for its minimization in IC manufacturing. Izv. vuzov. Elektronika = Proc. Univ. Electronics. 2025;30(5):597–606. (In Russ.). https://doi.org/10.24151/1561-5405-2025-30-5-597-606.
Financial source: the work has been supported by the Ministry of Education and Science of Russia (Agreement no. 075-03-2025-266 FSMR-2023-0002).

Mikhail S. Kulpinov
National Research University of Electronic Technology, (Russia, 124498, Moscow, Zelenograd, Shokin sq., 1)

Alexander A. Golishnikov
National Research University of Electronic Technology, (Russia, 124498, Moscow, Zelenograd, Shokin sq., 1)

Alexander G. Balashov
National Research University of Electronic Technology, (Russia, 124498, Moscow, Zelenograd, Shokin sq., 1)

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Information about the publication

UDK: 621.38.049.77
Publication type: Scientific article
Source lang: Russian
DOI: 10.24151/1561-5405-2025-30-5-597-606
RISC id: VJYTNG

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