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The possibility of applying porous silicon in creation of varicaps with high capacitance ratio, satisfying the requirements of microelectronic and macrosystem technology, has been investigated. The capacitor structures using the copper galvanic deposition to porous silicon pores have been presented. The morphological features of the experimental structures have been studied, the specific capacitance of varicaps has been determined. The obtained results demonstrate the prospects of application of varicaps based on porous silicon in integrated electronics.

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