Persons

The problem of analyzing and evaluating the structure of FPGA routing resources at early stages of the design flow presents great interest for researchers. Until now, an approach, consisting in passing the full design flow (logic synthesis, placement, routing) on a set of the test circuits with subsequent estimation of various parameters for each FPGA architecture being analyzed, had been dominant. Despite the high accuracy, this approach has a long runtime and requires lots of computing resources, as well as CAD tuned to the analyzed FPGA architecture. Modern FPGA contain more than a million logical gates, therefore, the application of such approach is inefficient. Today, more attention is paid to the development of various models, which allows to evaluate the structure of the routing resources at early stages without using the benchmark circuits. In this work an overview of the existing models and methods for analyzing the structure of FPGA routing resources has been presented. A comparison of the methods and models has been performed, the estimation of their efficiency and possibility of application for designing domestic FPGA has been made. It has been found that the most optimal approach for analyzing of arbitrary structures of the routing resources FPGA is the development and application of mixed methods. This will allow to obtain the accurate models as well as to significantly reduce the development and market entry time.

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With the reduction of the technological sizes of the transistors the influence of the circuit and process variations on the value of the element delays in the combinational circuits becomes significant. Due to variations of these parameters the uncertainty of the delays appears, which leads to the necessity of determination of the delay intervals. Another factor, affecting the design process of the CMOS circuits while turning to the nanometer technologies, the peak current, arising in the power rails when switching the inputs of gates, becomes. The peak current value is used for estimation of the voltage drop value in the power rails, which in its turn is necessary for calculating the width of the power rails and the width of the sleep-transistors in the power gating method. The problem of increasing the accuracy and reliability of the analysis of the performance of the peak current of the combinational circuits with consideration of simultaneous switching the inputs and logical correlations of signals, has been considered. It has been shown that the proposed approach to analysis of delays and peak current for IP blocks provides an increase in the accuracy of the upper bounds of the analyzed parameters up to 3% in comparison with the Spice simulation. The developed approach to the analysis of the peak current in CMOS circuits permits to reduce the pessimism of the upper bound by 2-3 times compared to the worst-case method. The practical importance of this work is to improve the accuracy of delays and peak currents simulation for CMOS combinational circuits at the timing and logical analysis. The developed methods can be used as an addition to the existing VLSI CAD tools for analyzing noise immunity and peak currents, characterizing IP blocks, and also for improving the accuracy of classical static analysis. To improve the accuracy of the interval estimates of the minimum delays and the maximum peak current, we develop simulation methods with simultaneous inputs switching. With respect to Spice simulation, the error of these methods does not exceed 3%. Compared to the results obtained without considering the simultaneous inputs switching, the reduction of the minimum delay reaches 50%, and the pessimistic estimation of the peak current in the combinational circuits decreases on the average by 50-55%.

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