Persons

With the reduction of the technological sizes of the transistors the influence of the circuit and process variations on the value of the element delays in the combinational circuits becomes significant. Due to variations of these parameters the uncertainty of the delays appears, which leads to the necessity of determination of the delay intervals. Another factor, affecting the design process of the CMOS circuits while turning to the nanometer technologies, the peak current, arising in the power rails when switching the inputs of gates, becomes. The peak current value is used for estimation of the voltage drop value in the power rails, which in its turn is necessary for calculating the width of the power rails and the width of the sleep-transistors in the power gating method. The problem of increasing the accuracy and reliability of the analysis of the performance of the peak current of the combinational circuits with consideration of simultaneous switching the inputs and logical correlations of signals, has been considered. It has been shown that the proposed approach to analysis of delays and peak current for IP blocks provides an increase in the accuracy of the upper bounds of the analyzed parameters up to 3% in comparison with the Spice simulation. The developed approach to the analysis of the peak current in CMOS circuits permits to reduce the pessimism of the upper bound by 2-3 times compared to the worst-case method. The practical importance of this work is to improve the accuracy of delays and peak currents simulation for CMOS combinational circuits at the timing and logical analysis. The developed methods can be used as an addition to the existing VLSI CAD tools for analyzing noise immunity and peak currents, characterizing IP blocks, and also for improving the accuracy of classical static analysis. To improve the accuracy of the interval estimates of the minimum delays and the maximum peak current, we develop simulation methods with simultaneous inputs switching. With respect to Spice simulation, the error of these methods does not exceed 3%. Compared to the results obtained without considering the simultaneous inputs switching, the reduction of the minimum delay reaches 50%, and the pessimistic estimation of the peak current in the combinational circuits decreases on the average by 50-55%.

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The transition to the level of the nanometer technologies leads to the new field in nanoelectronics, specifically the design based on the CMOS technology with 3D structure of the transistor. With decrease the size of transistors up to 32 nm and lower the application of FinFET technology becomes one of few methods to increase speed and to decrease the power consumption. This direction changes the design route and requires the development of new approaches, both in the logical and topological design. The traditional approach is based on the independent solution of the problems on the logical and physical levels. However, the combination of the logical and topological synthesis results in a significant increase of the problem dimension, which, in its turn, affects the designing time. The algorithm of the logical analysis and synthesis of microchip circuits with application of the FinFET technology while simultaneous solving the problems of the logical and topological synthesis has been developed. It has been offered to introduce the restrictions for the topological realization in simultaneous solving the problems of the logical and topological synthesis. The restrictions have been obtained from the regular topological template with a fixed layout in the lower layers. The proposed approach allows a hundreds to thousands times reduction of the design rules number, and the application of the IG FinFET transistors provides the best speed and power performances compared to the standard CMOS technology.

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