Persons

An improvement of the element base in the direction of reducing transistors in the source structures while simultaneously increasing the energy efficiency of the nodes being customized is an urgent problem. In the paper the energy-efficient triggers on CMOS-transistors with an inverter storage cell and a control circuit with Z -state: single-stage D -flip-flops, triggers with dynamic control, JK flip-flops, T -flip-flops, D -flip-flops with reset have been considered. The triggers are functional due to the combination of «strong» and «weak» transistors. The parameters of a D -flip-flop with an inverter storage cell have been investigated depending of the saturation current of the inverter MOS transistors in the positive feedback circuit. It has been shown that the change on the saturation current can significantly affect the propagation delay, dispersed power, the functioning thresholds and hysteresis. The presence of hysteresis increases the noise immunity of circuits on such elements.The circuits of the shifting register, asynchronous binary counter, twisted-ring counter, the synchronous binary counter, executed on the triggers with an inverter memory cell have been investigated. The comparison of parameters of the developed circuits with the circuits on standard logic elements has shown the advantage of circuits with an inverted memory cell in terms of the energy efficiency: significant advantage in terms of propagation delay 1.5-3.8 times, in terms of the propagation delay 1.1-2.0 times with respect to the number of transistors 1.7-2.0 times and in terms of energy topological parameter 3.0-8.2 times.

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Methods are required that can continuously increase the productivity and energy efficiency of semiconductor products and at the same time reduce the occupied minimum crystal area while maintaining its functionality to develop the growth rate of the modern microelectronics market. Therefore, at present, the tasks of integrating non-volatile elements - memristors into the well-known CMOS technology (complementary metal-oxide-semiconductor structure), of creating synthesis methods for the mentioned technology with memristor functional units (MeMOP-logic) are very relevant. A block method for the synthesis of hybrid MeMOS circuits has been presented. This method uses minterm maps, which allows synthesizing the MeMOS circuit and its optimization. The method has been presented on examples of the synthesis of combinational (XOR gate) and sequential (RS-trigger) circuits. The present work is devoted to the review of existing and the proposal of new options for solving synthesis problems of combinational and sequential integrated circuits with memristors. It has been shown that the average power dissipation of the RS -trigger is 7.7 mW for standard logic and 2.2 mW for logic on memristors. The power consumption of the circuit Excluding OR equal to 13 mW for standard logic and 9.2 mW for logic on memristors.

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The creation of methods for improving the trigger circuits in the direction of reducing the number of transistors and increasing their energy efficiency is an important task. For development of modern microelectronics the methods, allowing the synthesis of the energy-efficient trigger circuits, that have the least power dissipation, high speed and keep the minimum area of the crystal while maintaining their functionality, are required. In the work the block method of the synthesis of trigger circuits has been presented. It has been shown that the method uses the maps of minterms, which permits to simultaneously synthesize the trigger circuit and to optimize it. The method has been presented on the examples of the synthesis of one- and two-step D -, RS -, JK -, T -triggers. The comparison of the obtained triggers with standard trigger circuits on logic elements with respect to their energy efficiency has been performed. It has been shown that the use of the proposed method enables a significant a significant improvement (in average 2-4 times) of the energy efficiency of trigger circuits.

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