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The junctionless MOSFETs have a number of advantages compared to traditional ones in terms of the design simplicity, manufacturing technology and reducing the impact of short-channel effects upon the device characteristics. However, the known experimental nanowire JLT MOSFETs have high threshold currents due to parasitic bipolar transistor appearance in a closed state. A design of the device with a low impurity concentration in the working body and having the strongly doped contacts to the drain-source areas has been proposed. Using the device-technological modeling in the TCAD system, the influence of the contacts relative to the gate electrode on the main parameters of SOI MOS JLT has been studied. With the use of the Sentaurus Structure Editor the structural model of JLT MOSFETs with various thicknesses of a spacer, which determines the distance between the gate electrode and the contact drain-source areas, have been built, and the calculations of the I-V characteristics at a drain voltage of 0.1 V and 1.2 V have been performed. Transient VAC at the drain voltage 0.1 and 1.2 V have been calculated. By the transient characteristic with supply voltage at the drain of 1.2 V the curves of the threshold currents, the saturation currents and current-to-current ratio in the off state versus the size of the drain-source areas have been plotted. As a result of the research a new short-drain effect, dramatically reducing the threshold voltage, has been discovered and explained. This effect becomes apparent under the impact of SCR of the n + n transition between the contact and the drain on the channel region charge, when the distance between the gate electrode and the contact becomes less than 100 nm. While forming planar JLT MOSFETs according to the 90 nm technology it is necessary to create the drain-source regions with the size of 25 nm and to assign the concentration in the n-channel transistor 6 · 10 16 cm and in p-channel one - 5 · 10 16 cm. This will allow reducing the subthreshold currents of the device to 10 Aμm and to obtain a current ratio in the open and closed state 10. The most optimal size of the spacers thickness is from 160 to 340 nm, with which the influence of the contact n n transitions and sequential resistance of the drain-source regions on JLT MOSFET parameters, has been determined.

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Junctionless MOSFETs have a number of advantages over the traditional ones in terms of simplicity of design, manufacturing technology and reducing the impact of the short-channel effects on the device characteristics. However, the known experimental nanowire MOSFETs have high subthreshold currents due to the parasitic bipolar transistor appearance in the closed state. A structural model of a planar SOI in accordance with the technology standards of 90 nm and the route of mathematical modeling have been developed. The influence of the impurity concentration in the SOI MOSFET silicon film on the threshold voltage, the saturation currents and subthreshold currents using TCAD environment has been investigated. The investigation results show that if the impurity concentrations in the working body of the device is below 10 cm and there is no interband tunneling effect, and a parasitic bipolar transistor does not arise, the subthreshold currents decrease to 10 A/μm, while maintaining the saturation currents at an acceptable level, which is significantly lower than those of the conventional MOS transistors.

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The lateral junctionless MOSFET’s have a number of advantages compared to the conventional devices based on SOI structure. During the process of fabricating SOI structure and further technological operations of fabricating transistors, the change of the silicon film thickness is possible. In the work, using the device-technological modeling in the TCAD system the results of the studies on the influence of the SOI structure silicon film thickness on the main JLT parameters have been presented. It has been shown that to compensate the degradation of the device characteristics while changing the silicon film thickness it is necessary, respectively, to change the impurity concentration in silicon. For this, with the silicon film thicknesses less than 45 nm the level of the silicon film doping by the impurity higher than 10 cm is necessary.

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