The junctionless MOSFETs have a number of advantages compared to traditional ones in terms of the design simplicity, manufacturing technology and reducing the impact of short-channel effects upon the device characteristics. However, the known experimental nanowire JLT MOSFETs have high threshold currents due to parasitic bipolar transistor appearance in a closed state. A design of the device with a low impurity concentration in the working body and having the strongly doped contacts to the drain-source areas has been proposed. Using the device-technological modeling in the TCAD system, the influence of the contacts relative to the gate electrode on the main parameters of SOI MOS JLT has been studied. With the use of the Sentaurus Structure Editor the structural model of JLT MOSFETs with various thicknesses of a spacer, which determines the distance between the gate electrode and the contact drain-source areas, have been built, and the calculations of the I-V characteristics at a drain voltage of 0.1 V and 1.2 V have been performed. Transient VAC at the drain voltage 0.1 and 1.2 V have been calculated. By the transient characteristic with supply voltage at the drain of 1.2 V the curves of the threshold currents, the saturation currents and current-to-current ratio in the off state versus the size of the drain-source areas have been plotted. As a result of the research a new short-drain effect, dramatically reducing the threshold voltage, has been discovered and explained. This effect becomes apparent under the impact of SCR of the n + n transition between the contact and the drain on the channel region charge, when the distance between the gate electrode and the contact becomes less than 100 nm. While forming planar JLT MOSFETs according to the 90 nm technology it is necessary to create the drain-source regions with the size of 25 nm and to assign the concentration in the n-channel transistor 6 · 10 16 cm and in p-channel one - 5 · 10 16 cm. This will allow reducing the subthreshold currents of the device to 10 Aμm and to obtain a current ratio in the open and closed state 10. The most optimal size of the spacers thickness is from 160 to 340 nm, with which the influence of the contact n n transitions and sequential resistance of the drain-source regions on JLT MOSFET parameters, has been determined.
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