Junctionless MOSFETs have a number of advantages over the traditional ones in terms of simplicity of design, manufacturing technology and reducing the impact of the short-channel effects on the device characteristics. However, the known experimental nanowire MOSFETs have high subthreshold currents due to the parasitic bipolar transistor appearance in the closed state. A structural model of a planar SOI in accordance with the technology standards of 90 nm and the route of mathematical modeling have been developed. The influence of the impurity concentration in the SOI MOSFET silicon film on the threshold voltage, the saturation currents and subthreshold currents using TCAD environment has been investigated. The investigation results show that if the impurity concentrations in the working body of the device is below 10 cm and there is no interband tunneling effect, and a parasitic bipolar transistor does not arise, the subthreshold currents decrease to 10 A/μm, while maintaining the saturation currents at an acceptable level, which is significantly lower than those of the conventional MOS transistors.
1. Lee C., Afzalian A., Colinge J. Junctionless multigate field-effect transistor // Appl. Phys. Lett. – 2009. – Vol. 94. – No. 5. – Р. 346–358.
2. Nanowire transistors without junctions / Colinge J.P. et al. / Nature Nanotechnol. – 2010. – Vol. 5. – No. 3. – P. 225–229.
3. Gundapaneni S., Bajaj M., Kottantharayil A., Murali K. Effect of band-to-band tunneling on junctionless transistors // IEEE Trans. Electron Devices. – 2012. – Vol. 60. – No. 4. – P. 1021–1030.
4. Ghosh B., Bal P., Mondal P. A junctionless tunnel field effect transistor with low subthreshold slope // Springer Science. – 2013. – P. 487–499.
5. Migita S., Morita Y., Matsukawa T., Masahara M. Experimental demonstration of ultrashort-channel junctionless FETs utilizing atomically sharp V-grooves on SOI // IEEE Trans. Nanotechnol. – 2014. – Vol. 13. – No. 2. – P. 208–215.
6. Kumar M.J., Sahay S. Controlling BTBT induced parasitic BJT action in junctionless FETs using a hybrid channel // IEEE Transactions on Electron Devices. – 2016. – Vol. 63. – No. 8. – P. 3350–3353.
7. Королев М.А., Крупкина Т.Ю., Чаплыгин Ю.А. Приборно-технологическое моделиро-вание при разработке изделий микроэлектроники и микросистемной техники // Изв. вузов. Электроника. – 2005. – №4–5 – С. 64–71.