The JFET compact models used in commercial versions of SPICE-like software tools are oriented only to the standard range of –60 °C…+150 °C and are not suitable for simulation the electronic circuits in the range of cryogenic temperatures (below –120 °C). In the work the JEFT Low-T model, suitable for calculation of circuits in an extended temperature range, including the cryogenic ones (–200…+110 °C) has been developed. The model takes into account the changes in the I-V-characteristics due to the effect of the ultra-low temperature: an increase in the saturation voltage VDsat, a decrease in the pinch-off current Ip and the transconductance BETA, a negative slope LAMBDA on the output I-V-characteristics, an increase in the drain-source resistance RD due to the freeze-out effect, etc. For this purpose, the dependencies of the listed parameters on temperature have been additionally introduced. A procedure has been developed for extracting the SPICE-parameters of the JFET Low-T model from the results of measurements of a standard set of I-V-characteristics in the cryogenic temperature range. The error in simulation of the I-V-characteristics does not exceed 10–15% in the –200…+110 °C temperature range.
Konstantin O. Petrosyants
National Research University Higher School of Economics, Moscow, Russia; Institute for Design Problems in Microelectronics of Russian Academy of Sciences, Moscow, Russia
1. Cressler J.D., Mantooth H.A. (Eds.). Extreme environment electronics. – CRC Press, 2017. – 976 p.
2. Patterson R.L. Assessment of electronics for cryogenic space exploration missions // Cryogenics. – 2006. – Vol. 46. – N. 2–3. – P. 231–236.
3. Каталог разработок Российско-Белорусского центра аналоговой микросхемотехники / Н.Н. Прокопенко, С.Г. Крутчинский, Е.И. Старченко и др. – Шахты: ГОУ ВПО «ЮРГУЭС», 2010. – 479 с.
4. Kostopoulos K., Bucher M., Kayambaki M., Zekentes K. A compact model for silicon carbide JFET // Proc. of the 2nd Pan-Hellenic Conference on Electronics and Telecommunications (PACET'12). – 2012. – P. 1–4.
5. Design and performance of a modular low-radioactivity readout system for cryo-genic detectors in the CDMS experiment / Akerib D.S., P.D. Barnes, P.L. Brink et al. // Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spec-trometers, Detectors and Associated Equipment. – 2008. – Vol. 591. – N. 3. – P. 476–489.
6. Cryogenic performance of a low-noise JFET-CMOS preamplifier for HPGe detec-tors / A. Pullia, F. Zocca, S. Riboldi et al. // IEEE Transactions on Nuclear Science. – 2010. – Vol. 57(2). – P. 737–742.
7. Arnaboldi C., Fascilla A., Lund M.W., Pessina G. Temperature characterization of deep and shallow defect centers of low noise silicon JFETs // Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment. – 2004. – Vol. 517. – N. 1–3.– P. 313–336.
8. Shichman H., Hodges D.A. Modeling and simulation of insulatedgate field-effect transistor switching circuits // IEEE Journal of Solid-State Circuits. – 1968. – Vol. 3. – N. 3. – P. 285–289.
9. GaAs FET Device and Circuit Simulatin in Spice / H. Statz, P. Newman, I. Smith et al. // IEEE Trans. Electron Devices. – 1987. – Vol. ED-34. – P. 160–169.
10. Automation of parameter extraction procedure for Si JFET SPICE model in the −200…+110°C temperature range/ K.O. Petrosyants, M.R. Ismail-zade, L.M. Sambursky et al. // Proc. of Electronic and Networking Technologies (MWENT) / IEEE. – Moscow, 2018. – P. 1–5.
11. The accounting of the simultaneous exposure of the low temperatures and the penetrating radiation at the circuit simulation of the BiJFET analog interfaces of the sensors. / Dvornikov O. V., Dziatlau V. L., Prokopenko et al. // In Control and Communications (SIBCON), 2017 International Siberian Conference on / IEEE. – 2017. – P. 1–6.
12. Sze S.M. Physics of semiconductor devices. – N.Y.: J. Wiley and Sons, 1981. – 868 p.
13. Gutierrez-D E.A., Dean J., Claeys C. (Eds.). Low temperature electronics: phys-ics, devices, circuits, and applications. – Academic Press, 2000. – 964 p.
14. Sreelakshmi K., Satyam M. Estimation of low temperature characteristics of JFETs from their room-temperature characteristics // Cryogenics. – 1996. – Vol. 36. – N. 5. – P. 325–331.
15. Antognetti P., Massobrio G. Semiconductor device modeling with SPICE. – Se-cond Edition. – McGraw-Hill, Inc., 1993. – 479 p.