Persons

In production of the rad-hard electronic components base it is necessary to pay specific attention to single event effects because of the constantly increasing density of components on a chip. The effect of the embedded deep insulating N-well in 90-nm bulk CMOS structure on resistance to the thyristor effect, caused by the impact of heavy charged particles, has been investigated. The result of this study has to confirm or refute the expediency of using such technology in the memory cell design, which provides the elimination of latchup and has a minimum area. The influence of the deep N-well on the minimum spacing between the source and the well ties, which guarantees the latchup to occur, has been analyzed. It has been found that in case of small spacing between the N- and P-channel transistors of 0.12 μm, the isolation of P-well doesn’t give the expected result in terms of parasitic thyristor structure occurrence, since in this case the current flows near the surface region under STI and depends weakly on the base width of the pnp transistor. It has been shown that in case of the particle striking the source region of the N-channel transistor, the isolation of P-well may have a negative influence on the sensitivity of the bulk CMOS structure to the thyristor effect. In this case the threshold spacing between the source and well ties in the structure with deep well is approximately 0.6 μm lower than in the standard structure. The structure with deep N-well is not recommended for using in the rad-hard electronic components to mitigate the thyristor latchup.

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Currently polysilicon with high dopant concentration is used as a gate material in industrial manufacturing of MOST with the technological mode of up to 65 nm. The effects of quantization of inversion layer carriers in the substrate and of polysilicon gate depletion usually are taken into account by administering an effective electrical oxide thickness. At the same time, in the high-dopant polysilicon of the gate an additional quantum effect becomes apparent. It is associated with the quantization of the carriers near to high potential barrier and with the quantum dipole formation, leading to the shift of the MOS threshold voltage reduction. The effect of the polysilicon quantization has been simulated using the density gradient model included in the Synopsys Sentaurus TCAD package. It has been found that the shift of threshold voltage of MOS transistor is not dependent on the gate dielectric thickness. The shift of threshold voltage strongly depends on the impurity concentration in the substrate and lies in the range from 40 to 110 mV order, depending on the channel type, for the change of the impurity concentration from 10 to 10 cm. The shift of the threshold voltage is strongly dependent on the impurity concentration in the gate and is about 20 -140 mV for n-MOSFET and from 20 to 200 mV order for p-MOSFET for the change in the impurity concentration from 1 · 10 to 3 ·10 cm. It has been demonstrated that the local variation of the impurity concentration in the gate near the border of PolySi/SiO has a strong effect on the shift of the threshold voltage and this effect should be taken into account in the transistors physics modeling. The work results can be used for the model calibration of transistors current-voltage characteristics.

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