In production of the rad-hard electronic components base it is necessary to pay specific attention to single event effects because of the constantly increasing density of components on a chip. The effect of the embedded deep insulating N-well in 90-nm bulk CMOS structure on resistance to the thyristor effect, caused by the impact of heavy charged particles, has been investigated. The result of this study has to confirm or refute the expediency of using such technology in the memory cell design, which provides the elimination of latchup and has a minimum area. The influence of the deep N-well on the minimum spacing between the source and the well ties, which guarantees the latchup to occur, has been analyzed. It has been found that in case of small spacing between the N- and P-channel transistors of 0.12 μm, the isolation of P-well doesn’t give the expected result in terms of parasitic thyristor structure occurrence, since in this case the current flows near the surface region under STI and depends weakly on the base width of the pnp transistor. It has been shown that in case of the particle striking the source region of the N-channel transistor, the isolation of P-well may have a negative influence on the sensitivity of the bulk CMOS structure to the thyristor effect. In this case the threshold spacing between the source and well ties in the structure with deep well is approximately 0.6 μm lower than in the standard structure. The structure with deep N-well is not recommended for using in the rad-hard electronic components to mitigate the thyristor latchup.
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