Persons

The problem of analyzing and evaluating the structure of FPGA routing resources at early stages of the design flow presents great interest for researchers. Until now, an approach, consisting in passing the full design flow (logic synthesis, placement, routing) on a set of the test circuits with subsequent estimation of various parameters for each FPGA architecture being analyzed, had been dominant. Despite the high accuracy, this approach has a long runtime and requires lots of computing resources, as well as CAD tuned to the analyzed FPGA architecture. Modern FPGA contain more than a million logical gates, therefore, the application of such approach is inefficient. Today, more attention is paid to the development of various models, which allows to evaluate the structure of the routing resources at early stages without using the benchmark circuits. In this work an overview of the existing models and methods for analyzing the structure of FPGA routing resources has been presented. A comparison of the methods and models has been performed, the estimation of their efficiency and possibility of application for designing domestic FPGA has been made. It has been found that the most optimal approach for analyzing of arbitrary structures of the routing resources FPGA is the development and application of mixed methods. This will allow to obtain the accurate models as well as to significantly reduce the development and market entry time.

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The design features of the parameterized analog cells based on the matched matrix elements for SOI technology have been considered. The technique of creating such cells has been developed. The examples of the program code for building the parameterized analog cells, created based on the matched matrix elements , have been presented.

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The feedback implementation method based on the application of the gate comparator and the control of the charge, flowing through inductivity during switching the power key, as well as the method of study on similar devices, which is based on the analysis of discrete signals, have been described.

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Searching for new ways to improve the efficiency of integrated circuits (IC) led to the development of specialized heterogeneous configurable IC (FPGA) and systems-on-a-chip. Their key feature is an extended interpretation of standard cell library, containing ready-to-use IP cores along with standard cells. Specific customer designs require the flexibility of the configurable heterogeneous IC’s architecture and, therefore, automatic CAD clustering and placement algorithms configuration. The development of efficient configuration methods and algorithms is impossible without relying on the mathematical apparatus. In this work, such mathematical apparatus is provided. The authors described a set-theoretic model of a hierarchical project and formalized the hierarchical approach to the netlist, using the apparatus of mathematical logic, set and graph theories. The correspondence between the customers designs’ elements and FPGA’s elements has been formalized to provide fast clustering and placement configuration. The obtained results provide the basis for future efficient methods for automatic placement and clustering configuration.

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The design features of a current-mode logic encoder (CML) for a high-speed flash analog-to- digital converter have been considered. The basic characteristics of the logic elements on the current MOS switches, based on which the encoder has been designed, have been examined. The simulation results for the encoder on the current MOS switches have been presented.

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