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During production of modern technologies with high integration of elements some problems in the built-in memory testing and repair testing arise. An original architecture of fault-tolerant semiconductor memory with the specified multiplicity of fault detection has been suggested. It has been shown that not whole device is reserved but only the elements being mostly subject to failures and this reduces its mass and cost. The verification of the project of fault-tolerant memory with automatic recovery of efficiency in case of four failures has been carried out. The fault-tolerant memory project has been implemented into microcircuit M2S010-TQ144 of the system on chip SF2-Junior-KIT in the integrated medium of Microsemi Libero SoC v11.8 development. The proposed architecture of the fault-tolerant memory provides the automatic self-recovery in case of multiple faults of elements on board of the space vehicle control system using the built-in self-recovery device without application of fusion jumpers and an involvement of personnel. In the semiconductor memory in case of failure detection the automatic change of the data digits of the main data base storing cells, in which the faults took place, by the data coming from the reserve massive. This increases the reliability in case of executing multiple cycles of the efficiency recovery.

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In modern digital systems on a chip the amount of the built-in memory occupies a significant area, which causes the new manufacturing defects and reduces the percentage of the output of usable systems. The architecture of the built-in self-repair tools, providing the recovery of the system RAM on a chip in case of the multiple failures due to configuration of the main and back-up memory, has been proposed. The built-in means of self-repair of the system RAM on a chip contain a digital automatic machine and means of reconfiguration of the main and backup memory. The verification of the project of the built-in RAM self-repair tools with the automatic recovery of performance in case of four-fold failures has been performed. The proposed technical solution reduces the weight of the product compared to the devices with majority redundancy, since not all memory is entirely reserved, but only the main components that are most prone to failures. The restoration of the working state of the digital system memory on a chip is performed automatically without participation of personnel. The consumers of the built-in RAM self-repair tools can be large-scale manufacturers of the digital systems aimed at the market of industrial and special applications, including those for aerospace systems with long active life

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The I/О synchronization scheme plays an important role in achieving maximum speed and reliability of data transmission during memory operation. This paper presents the interface architecture of the DDR SDRAM test diagnostic device. It was demonstrated that the proposed interface components provide the formation of a bidirectional synchro signal for gating written and read data when performing test diagnostics of chips and DDR SDRAM memory devices. Compared to traditional methods, the proposed interface components were made on integrated electronic elements, which reduced the size and power consumption. It has been established that the use of a multiphase synchronization system to implement the interface eliminated the use of delay lines, the disadvantages of which are large dimensions and the complexity of changing the delay time. The interface components under consideration are intended for use in test diagnostics devices that have a multiprocessor structure, which increases the speed of forming test actions and reference reactions. The performed functional modeling and debugging of strobe signal generators confirmed the feasibility of the designs. The proposed interface of the test diagnostics device allows performing test diagnostics of modern high-speed chips and semiconductor memory modules at the operating frequency, which increases the reliability of the results obtained. Interface components can be used by manufacturers of test diagnostics tools for modern high-speed storage devices.

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