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It is necessary to reduce the configuration bit stream volume if there is a need to write several FPGA configurations to the ROM. This leads to decrease in the topological size of the ROM block on the chip. The article discusses the development of the mechanism of compression and decompression of the FPGA configuration bit stream. It has been shown that the stream of configuration data has some regularities. This is due to the presence of a large number of «forbidden» states in the configuration data set, when inadmissible connections of logical elements are formed. The algorithm of compression and decompression of the FPGA configuration bit stream has been proposed. The algorithm is based on the analysis of the FPGA architecture and the compilation of the conversion table using the prefix code commands. The advantage of the algorithm is the search for the most repetitive combinations based on the analysis of the FPGA architecture, instead of searching for the entropy of a random set of configuration data. Another advantage is the relative simplicity of the decoding algorithm, which saves hardware resources for the implementation of the decompression mechanism.

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For creating an optimal in terms of speed and flexibility programming the FPGA switching block it is necessary to estimate the minimum number of the commutation switches and their location in the connection matrix. In the work the problems of designing and evaluating the structure of the FPGA switching block have been considered. The algorithm for constructing and evaluating the structure of the FPGA switching blocks with the number of the interblock connections, based on the graph theory and combinatorial analysis, has been developed. It has been shown that not only the number of keys provides the commutation efficiency, but, also their location method.

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