Persons

The transition to the level of the nanometer technologies leads to the new field in nanoelectronics, specifically the design based on the CMOS technology with 3D structure of the transistor. With decrease the size of transistors up to 32 nm and lower the application of FinFET technology becomes one of few methods to increase speed and to decrease the power consumption. This direction changes the design route and requires the development of new approaches, both in the logical and topological design. The traditional approach is based on the independent solution of the problems on the logical and physical levels. However, the combination of the logical and topological synthesis results in a significant increase of the problem dimension, which, in its turn, affects the designing time. The algorithm of the logical analysis and synthesis of microchip circuits with application of the FinFET technology while simultaneous solving the problems of the logical and topological synthesis has been developed. It has been offered to introduce the restrictions for the topological realization in simultaneous solving the problems of the logical and topological synthesis. The restrictions have been obtained from the regular topological template with a fixed layout in the lower layers. The proposed approach allows a hundreds to thousands times reduction of the design rules number, and the application of the IG FinFET transistors provides the best speed and power performances compared to the standard CMOS technology.

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