Persons

The effect of noises in the power supply networks increases due to reduction of the power supply voltage and an increase of switching speeds of the digital circuits. Therefore, the design of voltage regulators with high power supply rejection ratio (PSRR) is substantial. The voltage regulator to provide high PSRR while the load current is being changed, depending on many factors, such as the technological process, temperature, operating mode, operating frequency and operating frequency of the circuits connected to the voltage regulator, has been proposed. In existing voltage regulators, independently from the current load value the pass device should have a large size to provide the possible maximum current, hence, it has strong capacitive coupling with the output, which affects PSRR. It has been shown that the proposed regulator changes the conductance of the pass device by enabling or disabling the additional parallel units in addition to controlling the gate-source voltage. It has been stated that the calibration maintains better PSRR for different load currents whereas the disabled units almost do not affect PSRR. Simulation using the analytical programs HSpice has shown the better results as compared to existing voltage regulators. The minimum PSRR has been improved from 17.53 dB to 22.1 dB for voltage regulator with the NMOS pass device, when the load current has two times decreased. The area of LDO voltage regulator has been 24% increased due to the added control block.

• Counter: 1264 | Comments : 0