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Ultra-reliable and safety control systems are built using various approaches, including calculations checking in blocks and nodes by different diagnostic sings. Traditionally, methods based on the introduction of modular redundancy are used for the synthesis of these systems. However, approaches can be applied that will reduce the structural redundancy of end devices. They can be implemented using the properties of self-dual functions together with code methods for calculations checking. In this work, the properties of self-dual fault-tolerant structures with calculations checking by parity code are analyzed. Two of the five structures are based on the use of duplication with calculations checking by parity code, and the other two, on the use of a single device with a block for distorted signals fixing implemented on the basis of the known Boolean method of signal correction. The fifth structure is a generalization of the fourth structure, where the calculations checking of parity is carried out for the blocks of addition and formation of correction functions. An experiment to analyze the detecting characteristics for an arbitrary combination device when introducing into its structure stuck-at faults at the outputs of internal elements is described. The analyzed structures make it possible to build fault-tolerant digital devices with reduced structural redundancy compared to widely applied approach based on the use of triple modular redundancy with majority correction. It was shown that the corrective ability of fault-tolerant structures is determined by the properties of the parity code chosen for calculations checking. The features of error detection of each structure under the action of stuck-at faults in their blocks have been established. They can be used in practice when implementing computing devices and systems on a modern programmable element base.

Key words: fault-tolerant devices, self-dual devices, error correction, calculations checking by parity code, self-dual testing
Published in: INFORMATION-COMMUNICATION TECHNOLOGIES
Bibliography link: Efanov D. V., Pogodina T. S. Self-dual fault-tolerant structures with calculations checking by parity code. II. Modeling the operation of digital devices in case of faults. Proc. Univ. Electronics, 2023, vol. 28, no. 6, pp. 838–853. https://doi.org/ 10.24151/1561-5405-2023-28-6-838-853. – EDN: FKEAPG.

Dmitry V. Efanov
Peter the Great St. Petersburg Polytechnic University, Russia, 195251, St. Petersburg, Politekhnicheskaya st., 29; Russian University of Transport, Russia, 127994, Moscow, Obraztsov st., 9, bld. 9

Tatiana S. Pogodina
Russian University of Transport, Russia, 127994, Moscow, Obraztsov st., 9, bld. 9

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UDK: 004.052.32+681.518.5
Publication type: Scientific article
Source lang: Russian
DOI: 10.24151/1561-5405-2023-28-6-838-853
RISC id: FKEAPG

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