In the control systems the FPGA systems more often are used as a central computing unit. However, high combination delays of the logic circuits on flexible logics and low maximum tact frequency of the FPGA systems restricts their application. The application of the behavioral hardware description in Verilog HDL for video processing on the hardware platform has been shown. An original algorithm has been proposed for the image features (key points) identifying, which can be used for the object search in the frame by a specified standard. The key points have been determined for the image areas, subjected to affine transformations, i.e. to rotation and scaling. The application of the FPGA systems is stipulated by the necessity of using the proposed algorithms in the systems being built-in with the camera resolution 640×480 pixels at 25 frames per second. The analysis of the frame processing speed by the algorithms, realized on other platforms has been carried out. The quantitative characteristics of the resources have been presented on an example of the Xilinx Spartan-6 FPGA family, their quality has been estimated by testing. The developed algorithm is characterized by the resistance, stability, invariance and its hardware implementation has comparable speed of fulfillment with respect to the most rapid algorithms of a similar class. Due to a small quantity of consumed FPGA resources there is the possibility of scaling and the efficiency improving.
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