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Generally, processing in real time is the important requirement for control systems that use a video stream as input information. Most commonly, this factor is one of the decisive when choosing a calculator. The use of FPGA systems allows not only to solve problems associated with runtime, but also to implement one of the most efficient options in terms of energy performance and functioning capability. In this work, a scheme that implements sequential access to all areas of each frame of the video stream is proposed. The resulting subsystem can be used, in particular, as part of hardware algorithms for filtering, detection, tracking and classification, that is, in cases where the algorithm solves the problem in order to find coordinates or it is necessary to apply a set of same-type actions over each area of the frame. A performance optimization algorithm for CAD Vivado has been developed. As a result, the actual scalability of the realized circuit is proved. It was demonstrated that the maximum achievable performance of this circuit is limited solely by the technology of a particular FPGA, and the amount of spent resources is minimal and linearly depends on the number of pixels that need to be accessed.

Key words: image processing, real-time processing, FPGA
Published in: CIRCUIT ENGINEERING AND DESIGN
Bibliography link: Sharikov A. I., Sharikova E. M. Scalable sample-and-hold FPGA system for pipelined video stream processing. Proc. Univ. Electronics, 2023, vol. 28, no. 2, pp. 202–211. https://doi.org/ 10.24151/1561-5405-2023-28-2-202-211

Anton I. Sharikov
National Research University of Electronic Technology, Russia, 124498, Moscow, Zelenograd, Shokin sq., 1

Elena M. Sharikova
National Research University of Electronic Technology, Russia, 124498, Moscow, Zelenograd, Shokin sq., 1

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UDK: 004.021:004.932
Publication type: Scientific article
Source lang: Russian
DOI: 10.24151/1561-5405-2023-28-2-202-211

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