The constructive and technological schemes of self-formation of completely self-combined vertically integrated transistor structures for ULIC have been presented. The exact positioning of the elements with nanometer sizes on a surface and at a certai...
The method for fabrication of HEMTs, in which T-gate is formed using the nanoimprint lithography technology, has been presented. The characteristics of the created GaAs pHEMT transistors have been investigated. The developed transistor has the gate b...
The models of electro-physical effects built-into Sentaurus TCAD have been tested. The models providing an adequate modeling of deep submicron high-k MOSFETs have been selected. The gate and drain leakage currents for 45 nm MOSFET with PolySi gate an...