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Nowadays, a big number of the decoding algorithms of the quasi-cyclic low-density parity-check code (QC-LDPC) and many variants of the apparatus implementation, based on the given algorithms, exist. Each of them has its advantages and drawbacks, related to the decoding efficiency, with the number of used apparatus resources and with a delay of the input data processing. The purpose of this paper is hardware implementation of QC-LDPC decoder with configurable latency and hardware resourses. The structure of the low-density quasi-cyclic parity-check code, presented in the standard IEEE 802.11ad, has been considered. The comparison of possible variants of the coder realization in the communications system has been performed. In MATLAB the model of the noise resistant coding system: QC-LDPC coder, the channel with additive white Gauss noise, the QC-LDPC decoder, has been implemented. Based on the given model the graph of the signal-to-noise ratio for the code being considered has been plotted. The noise resistant coding method considered is characterized by a lower delay and higher efficiency of decoding with equal size of the code word compared to other methods.

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