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Intellectual Property (IP) cores are developed and used to accelerate the custom integrated circuits design flow and improve their final characteristics. There are two types of FPGA IP-cores: hard IP-core and soft IP-core. Hard IP-cores have an exact location and pre-routed interconnects while soft IP-cores can be synthesized from logic elements and should be placed and routed. To use IP-cores in automated design flow of integrated circuits on FPGA and RSoC it is necessary to develop IP-core libraries that allow identifying blocks on every stage of flow. This work shows the various soft and hard IP-core libraries’ types and formats used as a part of design flow for Russian FPGA and RSoC. It describes the methods of designing libraries needed by CAD systems at the stages of logic synthesis, automatic technological mapping and layout synthesis. Also, it considers soft and hard IP-core libraries’ distinct features and the methods of their formation adjusted for the FPGA and RSoC architecture. The design methods have been proposed that allow designing of libraries necessary for automated implementation of hard as well as soft IP-cores using advantage of base FPGA and RSoC architecture.

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The existing means for designing automation are oriented, mainly, at technologies of western manufactures. As a result, a need in adaptation of available methods and means of designing the reconfigurable systems on chip and development of domestic specialized CAD devices for solving the actual tasks in this field appears. The methods for solving the interconnect routing problems combined with the logical resynthesis, considering the architecture of the reconfigurable system-on-chip (RSoC) based on FPGA of Almaz-14, have been proposed. In the chip the developers from JSC «NIIME» and PJSC «Micron» have created an extensive configuration options having no foreign analogs. The availability of a wide range of additional elements for configuring as well as the capabilities of logical resynthesis of the FPGA Almaz-14 microcircuit leads to the necessity of developing the new methods for routing the interconnects, which could take into account and use these architectural features. The efficient algorithm of automatic routing of interconnects for RSoC based on FPGA of Almaz-14 series based on the algorithm A*, of the modification of a classical algorithm of searching for the shortest path on graph, the Dijkstra’s algorithm, including the model of the mixed commutation graph, has been developed. For description of the variety of additional switching elements a special generalized mathematical model as well as a special command interface in Tcl language, which includes a list of configuration elements, their description and functionality, has been developed. The of result of the work is an improvement of the automated design efficiency using the developed and implemented in C language for optimal use of the configurations and route elements of FPGA, as well as of the mechanisms for the full and correct routing of interconnects.

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