Persons

Placement stage is one of the most crucial and time-consuming stages of design flow in the basis of reconfigurable systems-on-chip (RSoC). In this work the analysis of various approaches to solving the elements’ placement in the topological synthesis flow of digital circuits in the RSoC basis with an island hierarchical architecture has been presented. Various approaches of implementation of the placement algorithm using the simulated annealing method have been considered. The first approach represents the global placement of logic elements and sequential detailed placement within groups. The second approach is similar to the first one, but at the detailed placement the rearrangement of logic elements have been performed simultaneously in all groups. In the third approach the global placement step is absent and the rearrangement of the logic elements is not limited by the borders of the groups. The testing of the algorithms has been performed in the domestic RSoC basis. The experimental results demonstrate that usage of the third approach allows to increase the routability of the circuits being designed, to reduce the length of inter-connections, as well to improve the speed up to 49 %.

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