Persons

During functional logic modeling in the process of developing specialized large-scale integrated circuits (LSI) various tasks have to be solved. Currently, the domestic CAD systems lack the error localization subsystem at the stage of the functional-logical design. In the work the existing CAD methods have been analyzed, where the necessary minimum functionality for the error localization technique in the context of improving the «Kovcheg» CAD system had been considered. An effective method of localizing errors based on the requirements of the domestic process and the CAD analysis has been proposed. The formalization of the task of reducing the time for designing LSI has been presented. In addition, a diagram of the data of the developed error localization subsystem has been given, taking into account the features of the “Kovcheg” CAD system. These features, in particular, include the structure of the LSI projects and the peculiarities of storing information in them. When considering the dependence of the LSI development time on the degree of integration of the chip before and after embedding the error localization subsystem in the CAD system, the theoretical shortening of the LSI development time with these simplifications and averages is about 7% in ideal working conditions.

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