Persons

The interest to self-timed circuit engineering is related to super-large integrated circuits. The degree of integration of transistors on a chip increases making millions of gates and at the same time their sizes decrease. Therefore, the circuits, permitting to increase the degree and power efficiency with comparable performance, are urgent. The implementation of the circuit of asynchronous adder with the two-rail code and the indicator duration of transient on CMOS transistors has been proposed. The method of the circuit configuration of indicator duration, based on the formation of short pulses corresponding to presence of the transient, has been presented. The comparative analysis of the indicators performances has demonstrated a significant reduction of the number of components and reduced power consumption. The efficiency of the introduced circuits has been confirmed by simulation in CAD OrCAD using the program of circuit simulation PSpice.

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