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A gate dielectric is one of the crucial components of submicron MOS transistor structure which greatly affects its operation reliability. Transistor functionality loss, as well as a failure in the IC operation or a complete failure of the entire IC can be a result of dielectric breakdown. Therefore, the assessment of the gate dielectric defectiveness and its time to failure requires special attention. This paper considers a method for time to failure determination for MOS transistor gate dielectrics based on the time-dependent dielectric breakdown method. The time to failure is determined on the basis of the integral distribution of failures obtained by means of sampling of technological test structures measurements. Various parameter values are used that accelerate failure: high voltage and temperature. The Weibull distribution is used as a failure distribution statistic, and time to failure determination is carried out using a thermomechanical model ( E -model). The research has been performed on test structures represented by MOS capacitors with gate dielectric thickness of 5 nm. The test structures have been developed using the 65 nm technology and placed in a test chip on the same wafer with the integrated circuits. Software has been developed for the research that allows accelerated measurements in automatic mode. As a result of the conducted research, the parameters of the thermomechanical failure model have been determined; the dependencies of the gate dielectric time to failure on the operating conditions have been obtained. It has been found out that both hard and soft dielectric breakdowns can occur for the test structures under study. This method of control can be used to predict the long-term reliability of sub-100 nm MOS transistors gate dielectric, as well as for its production methods assessment.

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The methodology and an automated program, which allow using the accelerated measurements of the test structures composed of plates to identify the dielectric defects and to assess its operating time to failure, have been developed. The results of calculation of the dielectric defects with the account of the effect of the isolation and diffusion boundary have been presented. It has been shown that this technique can be used for monitoring the parameters of the manufacturing processes of the gate dielectric and forecasting the long-term reliability of MOS-transistors.

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