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Currently polysilicon with high dopant concentration is used as a gate material in industrial manufacturing of MOST with the technological mode of up to 65 nm. The effects of quantization of inversion layer carriers in the substrate and of polysilicon gate depletion usually are taken into account by administering an effective electrical oxide thickness. At the same time, in the high-dopant polysilicon of the gate an additional quantum effect becomes apparent. It is associated with the quantization of the carriers near to high potential barrier and with the quantum dipole formation, leading to the shift of the MOS threshold voltage reduction. The effect of the polysilicon quantization has been simulated using the density gradient model included in the Synopsys Sentaurus TCAD package. It has been found that the shift of threshold voltage of MOS transistor is not dependent on the gate dielectric thickness. The shift of threshold voltage strongly depends on the impurity concentration in the substrate and lies in the range from 40 to 110 mV order, depending on the channel type, for the change of the impurity concentration from 10 to 10 cm. The shift of the threshold voltage is strongly dependent on the impurity concentration in the gate and is about 20 -140 mV for n-MOSFET and from 20 to 200 mV order for p-MOSFET for the change in the impurity concentration from 1 · 10 to 3 ·10 cm. It has been demonstrated that the local variation of the impurity concentration in the gate near the border of PolySi/SiO has a strong effect on the shift of the threshold voltage and this effect should be taken into account in the transistors physics modeling. The work results can be used for the model calibration of transistors current-voltage characteristics.

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