Due to the technology development and decreasing supply voltages, undesirable effects on sensitive analog signals like noise, kickback are becoming more expressed. Mentioned issues are present in analog to digital converters (ADC) and design of high accuracy ADCs is becoming more complex. In this work, a circuit was proposed based on a latch comparator and comparison range shifter, which increased the accuracy of a two-step flash ADCs by excluding the chance of incorrect coarse conversion, when the input analog voltage is close to separating points of the comparison range of first stage of the ADC. The proposed circuit was constructed using an 16nm FinFET process, the simulations were done with HSpice simulator. The idea was to increase the accuracy of an already designed two-step flash ADC by adding the proposed circuit, which was done by shifting the comparison range during the coarse conversion, for the difference of input voltage and separating points not to be smaller than the offset of comparators used in ADC. It was established that the use of the proposed circuit increased the comparison time, as the sampled input analog voltage firstly should be compared with comparison range separating points, but on the other hand the ADC became more sensitive to its input change (up to 4mV offset) and was performing stable, excluding the chance of wrong coarse conversion. It has been shown that proposed architecture allows avoiding the use of low offset and high accuracy complex comparators in two-step flash ADCs, which greatly reduces the layout area.
1. Razavi B. Design of Analog CMOS Integrated Circuits. 2nd ed. New York, McGraw-Hill, 2015. 782 p.
2. Sedra A.S., Smith K.C. Microelectronic Circuits. 7th ed. Oxford, Oxford University Press, 2014. 1488 p.
3. Baker R.J. CMOS Circuit Design, Layout, and Simulation. 3rd ed. Hoboken, NJ, Wiley, 2010. 1173 p.
4. Razavi B. Principle of Data Conversion System Design. New York, Chichester, Weinheim et al., Wiley-IEEE Press, 1995. 272 p.
5. Gustavsson M., Wikner J.J., Nianxiong Tan. CMOS Data Converters for Communications. New York, Springer, 2002. xxii, 378 p. DOI: https://doi.org/10.1007/b117690
6. Katyal V., Geiger R.L., Chen D.J. A new high precision low offset dynamic comparator for high resolution high speed ADCs. 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 4–7 Dec. 2006. Piscataway, NJ, IEEE, 2006, pp. 5–8. DOI: https://doi.org/10.1109/APCCAS.2006.342249
7. Khosrov D. A new offset cancelled latch comparator for high-speed, low-power ADCs. 2010 IEEE Asia Pacific Conference on Circuits and Systems. Kuala Lumpur, IEEE, 2010, pp. 13–16. DOI: https://doi.org/ 10.1109/APCCAS.2010.5774892
8. Liu J., Li F., Li W., Jiang H., Wang Z. A flash ADC with low offset dynamic comparators. 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, IEEE, 2017, pp. 1–2. DOI: https://dx.doi.org/10.1109/EDSSC.2017.8126480
9. Nasrollahpour M., Sreekumar R., Hamedi-Hagh S. Low power comparator with offset cancellation technique for Flash ADC. 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Giardini Naxos, IEEE, 2017, pp. 1–4. DOI: https://doi.org/10.1109/SMACD.2017.7981602
10. Oh D., Kim J., Jo D., Kim W., Chang D., Ryu S. A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 x time-domain interpolating flash ADC with sequential slope-matching offset calibration. IEEE Journal of Solid-State Circuits, 2019, vol. 54, no. 1, pp. 288–297.
11. Yang X., Bae S.-J., Lee H.-S. An 8-bit 2.8 GS/s flash ADC with time-based offset calibration and interpolation in 65 nm CMOS. IEEE 45th European Solid State Circuits Conference (ESSCIRC), Poland, IEEE, 2019, pp. 305–308.
12. Gevorgyan V. A small area and low power voltage comparator based on a latch with configurable sensitivity. Proceedings of National Academy of Sciences of Republic of Armenia and National Polytechnic University of Armenia, Series of Technical Sciences, 2020, pp. 30–39.
13. HSPICE Reference Manual. Synopsys Inc., 2017. 846 p.