An analog-to-digital converter (ADC) based on a phase-locked loop (PLL) is characterized by the intermediate conversion of voltage into pulse duration and does not have high requirements for passive circuit elements. Compensation of errors in the nominal values of passive circuit elements and resistance to temperature changes are some of an ADC based on a PLL circuit’s advantages over known analogs. Despite the low requirements for errors in the nominal values of passive elements, when designing an ADC based on a PLL loop it is necessary to consider the oscillatory properties of the PLL loop. In this work, it was demonstrated that the circuit elements’ parameters calculation must be carried out in such a way that the effects of the measured voltage and the ratings of the passive circuit elements do not lead to an exit from the balanced state and the appearance of a parasitic oscillatory PLL circuit. The implementation of a mathematical model of PLL for ADC based on the transfer function of the 2nd order oscillatory circuit using the transfer coefficients of the PLL circuit blocks has been presented. It was demonstrated that this approach allows evaluating the oscillatory properties and calculating the ratings of the passive circuit elements for stable operation of the oscillatory PLL circuit, as well as assessing the range of compensation for negative feedback.