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With the IC elements transition to critical size region of less than 100 nm, two-dimensional shapes of element structures manufactured during fabrication cycle are changed to three-dimensional complex shapes. These are different gate structures of MOS transistors, oxide and nitride photolithography masks, “fin” gate transistors (FinFET), gate-all-around transistors (GAAFET) and others. Process validation, besides requirements to critical sizes of elements in the two-dimensional plane, also includes requirements to precision of full profile measurements. Despite the wide variety of currently developed linear dimensions and surface profile measurement techniques, not all of them can be applied to three-dimensional profile control of fabricated structures. In this work, based on literature data analysis the features of widely used techniques for measurement of linear sizes and topology elements are displayed, and the difficulties in employing them to control a three-dimensional profile are elicited. The promising measurement techniques currently being introduced in the IC fabrication have been considered.
Ilya V. Nelyubin
National Research University of Electronic Technology, Russia, 124498, Russia, Moscow, Zelenograd, Shokin sq., 1
Michail G. Putrya
National Research University of Electronic Technology, Russia, 124498, Russia, Moscow, Zelenograd, Shokin sq., 1

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