An improvement of the element base in the direction of reducing transistors in the source structures while simultaneously increasing the energy efficiency of the nodes being customized is an urgent problem. In the paper the energy-efficient triggers on CMOS-transistors with an inverter storage cell and a control circuit with Z -state: single-stage D -flip-flops, triggers with dynamic control, JK flip-flops, T -flip-flops, D -flip-flops with reset have been considered. The triggers are functional due to the combination of «strong» and «weak» transistors. The parameters of a D -flip-flop with an inverter storage cell have been investigated depending of the saturation current of the inverter MOS transistors in the positive feedback circuit. It has been shown that the change on the saturation current can significantly affect the propagation delay, dispersed power, the functioning thresholds and hysteresis. The presence of hysteresis increases the noise immunity of circuits on such elements.The circuits of the shifting register, asynchronous binary counter, twisted-ring counter, the synchronous binary counter, executed on the triggers with an inverter memory cell have been investigated. The comparison of parameters of the developed circuits with the circuits on standard logic elements has shown the advantage of circuits with an inverted memory cell in terms of the energy efficiency: significant advantage in terms of propagation delay 1.5-3.8 times, in terms of the propagation delay 1.1-2.0 times with respect to the number of transistors 1.7-2.0 times and in terms of energy topological parameter 3.0-8.2 times.