The issues of creating the schemes of the quartz generators (QG), intended for implementation in CMOS 0.18 micron technology, have been considered. The options of the QG circuit design with low noise, which are tolerant to 2xVDD voltage, have been offered. Based on the analysis of the nature of the automatic gain control of CMOS inverters the time minimization of the QG exit to the operating mode has been carried out.