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When using weight-based sum codes of digits fr om a natural series of numbers in a ring of deductions according to a given module, for the synthesis of self-checking discrete devices it is necessary to control whether the generated codewords belong to a specific code. This is done using detectors or code checkers. The latter are built by self-checking, which is important for creating fully self-checking structures. In this work, the methods of synthesizing checkers for sum codes based on the methods of discrete mathematics and the theory of Boolean functions are proposed. Approaches to synthesizing weight-based sum code checkers are described. It is shown that checkers are effectively built on a two-stage structure, including an encoder and a comparator. A comparator in such a structure is a standard device synthesized on the basis of a k–1 two-rail signal compression module, wh ere k is the number of check code characters. The synthesis of encoders of weight-based sum codes was performed, since different implementations of encoders will have various technical characteristics i. e. indicators of structural redundancy, performance, controllability. A method for synthesizing encoders of the codes used in the structures of checkers is proposed. A comparison of the complexity indicators of the implementation of encoders of the considered class of sum codes with encoders for other sum codes is given. It has been demonstrated that encoders of sum codes of the weight coefficients of digits from a natural series of numbers in the ring of deductions according to a given modulus have simpler structures than encoders of sum codes of the weight coefficients of digits from a natural series of numbers with the exception of powers of two. The proposed method for synthesizing encoders of weight-based sum соdes of digits from a natural series of numbers in the ring of deductions for this module allows in practice to implement self-checking checkers of these codes, effectively used in the synthesis of self-checking discrete devices.

Key words: systems of technical diagnostics of discrete devices, modular weight-based sum codes, sequence of weight coefficients, natural series
Published in: INFORMATION-COMMUNICATION TECHNOLOGIES
Bibliography link: Efanov D. V., Yelina Y. I. Sum codes of the weight coefficients of digits from a natural series of numbers. II. Synthesis of sum code checkers. Izv.vuzov. Elektronika = Proc. Univ. Electronics. 2025;30(4):497–507. (InRuss.). https://doi.org/10.24151/1561-5405-2025-30-4-497-507.

Dmitry V. Efanov
SPbPU (Russia, 195251, St. Petersburg, Politekhnicheskaya st., 29); RUT (Russia, 127994, Moscow, Obraztsov st., 9, bld. 9); TDTU (Uzbekistan, 100167, Tashkent, 1st Dr Temiryulchilar, 1)

Yeseniya I. Yelina
SPbPU (Russia, 195251, St. Petersburg, Politekhnicheskaya st., 29)

1. Мехов В. Б., Сапожников В. В., Сапожников Вл. В. Контроль комбинационных схем на основе модифицированных кодов с суммированием. Автомат.ителемех. 2008;(8):153–165. EDN: NBKMJT.

Mekhov V. B., Sapozhnikov V. V., Sapozhnikov V. V. Checking of combinational circuits basing on modification sum codes. Autom.RemoteControl. 2008;69(8):1411–1422. https://doi.org/10.1134/S0005117908080134

2. Мехов В. Б.Построение тестов для взвешенных кодов. Автоматика и телемеханика железных дорог России. Новая техника и новые технологии: сб. науч. тр. Под ред. Вл. В. Сапожникова. СПб.: ПГУПС; 2007, с. 81–89.

Mekhov V. B. Building tests for weighted codes. In: Avtomatika i telemekhanika zheleznykh dorog Rossii. Novaya tekhnika i novye tekhnologii: collection of scientific papers. Ed. by Vl. V. Sapozhnikov. St. Petersburg: St. Petersburg State Transport University; 2007, pp. 81–89. (In Russ.).

3. Сапожников В. В., Сапожников Вл. В., Ефанов Д. В. Коды с суммированием для систем технического диагностирования: в 2 т. Т. 2: Взвешенные коды с суммированием. М.: Наука; 2021. 455 с. EDN: KIHERR.

Sapozhnikov V. V., Sapozhnikov Vl. V., Efanov D. V. Sum codes for technical diagnostics systems: in 2 vol. Vol. 2: Weight-based sum codes. Moscow: Nauka Publ.; 2021. 455 p. (In Russ.).

4. Ефанов Д. В., Елина Е. И. Коды с суммированием весовых коэффициентов разрядов из натурального ряда чисел. I. Свойства кодов с суммированием. Изв. вузов. Электроника. 2025;30(3):344–361. https://doi.org/10.24151/1561-5405-2025-30-3-344-361. EDN: FCOVRA.

Efanov D. V., Yelina Y. I. Sum codes of weight coefficients of digits from a natural series of numbers. I. Properties of sum codes. Izv.vuzov. Elektronika = Proc. Univ. Electronics. 2025;30(3): 344–361. (InRuss.). https://doi.org/10.24151/1561-5405-2025-30-3-344-361

5. Согомонян Е. С., Слабаков Е. В.Самопроверяемые устройства и отказоустойчивые системы. М.: Радиоисвязь; 1989. 208 с.

Sogomonyan E. S., Slabakov E. V. Self-checking devices and fault-tolerant systems. Moscow: Radioisvyaz’ Publ.; 1989. 208 p. (InRuss.).

6. Сапожников В. В., Сапожников Вл. В.Самопроверяемые дискретные устройства. СПб.: Энергоатомиздат; 1992. 224 с. EDN: UGZVWP.

Sapozhnikov V. V., Sapozhnikov Vl. V. Self-checkingdiscretedevices.St. Petersburg: EnergoatomizdatPubl.; 1992. 224 p. (InRuss.).

7. Сапожников В. В., Сапожников Вл. В. Самопроверяемые тестеры для равновесных кодов. Автомат.ителемех. 1992;(3):3–35.

Sapozhnikov V. V., Sapozhnikov Vl. V. Self-checking checkers for equilibrium codes. Autom.Remote Control.1992;53(3):321–348.

8. Carter W. C., Duke K. A., Schneider P. R. Self-checking error checker for two-rail coded data. Patent US, 3559167A, 26.01.1971.

9. Harris D. M., Harris S. L.Digital design and computer architecture.2nded. SanFrancisco, CA: MorganKaufmann; 2012. 720 p.

10. Ефанов Д. В., Елина Е. И. Модульные коды с суммированием с последовательностью весовых коэффициентов, образующей натуральный ряд чисел за исключением степеней двойки. Автоматиканатранспорте. 2024;10(3): 296–330. https://doi.org/10.20295/2412-9186-2024-10-03-296-330. EDN: AFQVKW.

Efanov D. V., Elina E. I. Modular sum codes with a sequence of weight coefficients forming a natural number series excluding powers of two. Avtomatika na transporte = Transport Automation Research. 2024;(3):296–300. (In Russ.). https://doi.org/10.20295/2412-9186-2024-10-03-296-330

11. On-Line Encyclopedia of Integer Sequences. Available at: https://oeis.org/ (accessed: 12.03.2025).

12. Sentovich E. M., Singh K. J., Moon C., Savoj H., Brayton R. K., Sangiovanni-Vincentelli A. Sequential circuit design using synthesis and optimization. In: Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors,11–14 Oct. 1992. Cambridge, MA: IEEE; 1992, pp. 328–333. https://doi.org/10.1109/ICCD.1992.276282

13. Sentovich E. M., Singh K. J., Lavagno L., Moon C., Murgai R., Saldanha A. et al. SIS: A system for sequential circuit synthesis: Tech. rep. No. UCB/ERL M92/41.US Berkeley Electrical Engineering & Computer Sciences. 04.05.1992. Available at: https://www2.eecs.berkeley.edu/Pubs/TechRpts/1992/2010.html (14.05.2025).

14. Piestrak S. J. Design of self-testing checkers for unidirectional error detecting codes. Wrocław: Oficyna Wydawnicza Politechniki Wrocłavskiej; 1995. 111 p.

15. Göessel M., Ocheretny V., Sogomonyan E., Marienfeld D.New methods of concurrent checking. Dordrecht: Springer; 2008. viii, 182 p. https://doi.org/10.1007/978-1-4020-8420-1

16. Ефанов Д. В., Елина Е. И. Синтез кодеров взвешенных кодов с суммированием в кольце вычетов по заданному модулю. Программнаяинженерия. 2024;15(6):296–307. https://doi.org/10.17587/prin.15.296-307. EDN: AGBYKA.

Efanov D. V., Yelina Y. I. Synthesis of weight-based code encoders with summation in the ring of residues for a given modulus.Programmnaya ingeneria = Software Engineering. 2024;15(6):296–307. (In Russ.). https://doi.org/10.17587/prin.15.296-307

17. Сапожников В. В., Сапожников Вл. В., Ургансков Д. И. Универсальные структуры двоичных счетчиков единиц по произвольному модулю счета. Электронноемоделирование. 2002;24(4):65–81.

Sapozhnikov V. V., Sapozhnikov Vl. V., Urganskov D. I. Universal structures of binary unit counters for an arbitrary invoice module. Elektronne modelûvannâ = Electronic Modeling. 2002;24(4):65–81. (In Russ.).

18. Сапожников В. В.,Сапожников Вл. В., Ургансков Д. И. Блочная структура двоичного счетчика единиц по произвольному модулю счета. Электронное моделирование. 2005;27(4):65–81.

Sapozhnikov V. V., Sapozhnikov Vl. V., Urganskov D. I. Block structure of a binary unit counter for an arbitrary invoice module. Elektronne modelûvannâ = Electronic Modeling. 2005;27(4):65–81. (In Russ.).

19. Saposhnikov V. V., Saposhnikov Vl. V., Urganskov D. I. Composite structure of binary counter of ones arbitrary modulo. In: Proceedings of East-West Design & Test Workshop (EWDTWʼ05), 15–19 Sep. 2005. Odessa: IEEE; 2005, pp. 102–106.

20. Saposhnikov V. V., Saposhnikov Vl. V., Urganskov D. I. Multistage regular structure of binary counter of ones arbitrary modulo. In: Proceedings of East-West Design & Test Workshop (EWDTWʼ06), 15–19 Sep. 2006. Sochi: IEEE; 2006, pp. 287–290.

21. Suprun V. P., Gorodecky D. A. Realization of addition and multiplication operations in unitary codes.Aut. Control Comp. Sci. 2010;44(5):292–301. https://doi.org/10.3103/S014641161005007X

22. Suprun V. P. Single-level schematic realization of basic operations of modular arithmetic in unitary codes. Aut.ControlComp. Sci. 2011;45(2):70–79. https://doi.org/10.3103/S0146411611020088

23. Балака Е. С., Городецкий Д. А., Рухлов В. С., Щелоков А. Н. Разработка высокоскоростных сумматоров по модулю на базе комбинационных сумматоров с параллельным переносом. Изв. ЮФУ. Техническиенауки. 2016;(6):158–169. EDN: WLXBST.

Balaka E. S., Gorodecky D. A., Rukhlov V. S., Schelokov A. N. Design and synthesis of high speed modulo adders using parallel prefix structure. Izv.YuFU. Tekhnicheskie nauki = Izvestiya SFedU. Engineering Sciences.2016;(6):158–169. (In Russ.).

Information about the publication

UDK: 004.052.32+681.518.5
Publication type: Scientific article
Source lang: Russian
DOI: 10.24151/1561-5405-2025-30-4-497-507
RISC id: EZHVOK

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