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The circuits’ check by their simulation with transistor level simulators of SPICE type doesn’t allow handling the analysis of modern VLSI. It is possible to decrease the labor intensity of circuit testing by replacing the general-purpose simulation of VLSI (or part of VLSI) with less demanding logic simulation. In this work, the problem of extracting high-level structure at the level of logical elements from a transistor level circuit is considered. It has been established that obtaining such a representation significantly reduces the execution time of VLSI topology verification at the design stage and serves as the basis for IC redesign and reverse engineering to detect unauthorized attachments. The task is to decompile a flat netlist of a CMOS circuit in order to construct a hierarchical structural netlist, the components of which are logic gates and their subcircuits. Descriptions of the original flat and resulting hierarchical CMOS circuits are presented in SPICE format. Methods are proposed for extracting subcircuits of pass transistor logic, representing transmission gates and circuits built on their basis. It was demonstrated that in some cases, pass transistor logic allows complex elements such as multiplexers and XOR gates to be implemented with simpler transistor circuits than traditional static CMOS logic provides. The proposed methods for structural recognition of transmission gates and circuits based on them are implemented in C++ as a part of a program for decompiling a flat transistor netlists in SPICE format. The program has been tested on practical transistor level circuits. The result of the decompilation program running is a hierarchical SPICE description, which includes models of all identified logical elements.

Key words: CMOS circuit, pass transistor logic, subcircuit extraction problem, decompilation of CMOS circuit descriptions, SPICE format
Published in: CIRCUIT ENGINEERING AND DESIGN
Bibliography link: Cheremisinov D. I., Cheremisinova L. D. Methods of structural recognition of subcircuits of pass transistor logic in CMOS circuits. Proc. Univ. Electronics, 2025, vol. 30, no. 1, pp. 51–63. https://doi.org/10.24151/1561-5405-2025-30-1-51-63

Dmitry I. Cheremisinov
The United Institute of Informatics Problems of the National Academy of Sciences of Belarus (Belarus, 220012, Minsk, Surganov st., 6)

Liudmila D. Cheremisinova
The United Institute of Informatics Problems of the National Academy of Sciences of Belarus (Belarus, 220012, Minsk, Surganov st., 6)

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Information about the publication

UDK: 519.714.5
Publication type: Scientific article
DOI: 10.24151/1561-5405-2025-30-1-51-63
RISC id: BBYYLF

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